From f9b4bda441bb949b44482c65cd1d4fcfcdfbfa13 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Mon, 9 Sep 2019 17:50:13 -0400 Subject: [PATCH] MLK-22573-2 gpu: imx: dpu-blit: Do not initialize STORE9_STATIC register The bit DIV0 of register STORE9_STATIC is used as a control bit to fix the unsynchronization issue bewteen two display streams in FrameGen side-by-side mode, which is introduced from an ECO operation for the display controller. The bit has to be one when the side-by-side mode is enabled. And, it has to be zero when the mode is disabled, otherwise, a single display stream cannot startup correctly. Since the DPU common driver initializes the register for us at the driver probe stage and system resume stage, we may remove the same initialization logic of our own. Without this patch, as the DPU blit engine DRM driver is resumed relatively late, the bit would be overwritten to be zero at the driver's ->resume() callback, which causes the display controller cannot be correctly resumed from FrameGen side-by-side mode and content ExtDst shadow load done event from the slave stream won't come. Signed-off-by: Liu Ying (cherry picked from commit 785a8705624e114f4f3d3d0836826130fb57b46f) --- drivers/gpu/imx/dpu-blit/dpu-blit.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/gpu/imx/dpu-blit/dpu-blit.c b/drivers/gpu/imx/dpu-blit/dpu-blit.c index f4a728f52507..4646d041bd75 100644 --- a/drivers/gpu/imx/dpu-blit/dpu-blit.c +++ b/drivers/gpu/imx/dpu-blit/dpu-blit.c @@ -255,7 +255,7 @@ EXPORT_SYMBOL(dpu_be_wait); static void dpu_be_init_units(struct dpu_bliteng *dpu_be) { u32 staticcontrol; - u32 pixengcfg_unit_static, pixengcfg_unit_dynamic; + u32 pixengcfg_unit_dynamic; staticcontrol = 1 << FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT | @@ -306,18 +306,6 @@ static void dpu_be_init_units(struct dpu_bliteng *dpu_be) STORE9_STATICCONTROL_RESET_VALUE; dpu_be_write(dpu_be, staticcontrol, STORE9_STATICCONTROL); - /* Safety_Pixengcfg Static */ - pixengcfg_unit_static = - 1 << PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT | - 0 << PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT | - PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE << - PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT | - PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION << - PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT | - PIXENGCFG_DIVIDER_RESET << - PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT; - dpu_be_write(dpu_be, pixengcfg_unit_static, PIXENGCFG_STORE9_STATIC); - /* Safety_Pixengcfg Dynamic */ pixengcfg_unit_dynamic = PIXENGCFG_CLKEN__AUTOMATIC << PIXENGCFG_CLKEN_SHIFT | -- 2.17.1