From f9a3e9564ea3377024ad2c3bb314eb69ac491f82 Mon Sep 17 00:00:00 2001
From: Liu Ying <victor.liu@nxp.com>
Date: Wed, 7 Jun 2017 17:55:34 +0800
Subject: [PATCH] MLK-15001-38 arm64: dtsi: fsl-imx8qxp: MIPI DSI PD should be
 contained by DC PD

The MIPI DSI power domains are the child power domains of DC power domain.
So, let's wrap the MIPI DSI power domains by DC power domain.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 99 ++++++++-----------
 1 file changed, 43 insertions(+), 56 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 501773d25dee..d638dea9d1c6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -590,72 +590,59 @@
 			};
 		};
 
-		pd_dc: dc-power-domain {
+		pd_dc0: PD_DC_0 {
 			compatible = "nxp,imx8-pd";
-			reg = <SC_R_LAST>;
+			reg = <SC_R_DC_0>;
 			#power-domain-cells = <0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			pd_dc0: dc0-power-domain {
-				name = "dc0-power-domain";
-				reg = <SC_R_DC_0>;
+			pd_mipi_dsi0: PD_MIPI_0_DSI {
+				reg = <SC_R_MIPI_0>;
 				#power-domain-cells = <0>;
-				power-domains =<&pd_dc>;
-			};
-		};
-
-		pd_mipi_dsi0: PD_MIPI_0_DSI {
-			compatible = "nxp,imx8-pd";
-			reg = <SC_R_MIPI_0>;
-			#power-domain-cells = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 
-			pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 {
-				name = "mipi0_dsi_i2c0";
-				reg = <SC_R_MIPI_0_I2C_0>;
-				#power-domain-cells = <0>;
-				power-domains =<&pd_mipi_dsi0>;
-			};
-			pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 {
-				name = "mipi0_dsi_i2c1";
-				reg = <SC_R_MIPI_0_I2C_1>;
-				#power-domain-cells = <0>;
-				power-domains =<&pd_mipi_dsi0>;
-			};
-			pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 {
-				name = "mipi0_dsi_pwm0";
-				reg = <SC_R_MIPI_0_PWM_0>;
-				#power-domain-cells = <0>;
-				power-domains =<&pd_mipi_dsi0>;
+				pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 {
+					reg = <SC_R_MIPI_0_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
+				pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 {
+					reg = <SC_R_MIPI_0_I2C_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
+				pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 {
+					reg = <SC_R_MIPI_0_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
 			};
-		};
-
-		pd_mipi_dsi1: PD_MIPI_1_DSI {
-			compatible = "nxp,imx8-pd";
-			reg = <SC_R_MIPI_1>;
-			#power-domain-cells = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 
-			pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 {
-				name = "mipi1_dsi_i2c0";
-				reg = <SC_R_MIPI_1_I2C_0>;
-				#power-domain-cells = <0>;
-				power-domains =<&pd_mipi_dsi1>;
-			};
-			pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 {
-				name = "mipi1_dsi_i2c1";
-				reg = <SC_R_MIPI_1_I2C_1>;
-				#power-domain-cells = <0>;
-				power-domains =<&pd_mipi_dsi1>;
-			};
-			pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 {
-				name = "mipi1_dsi_pwm0";
-				reg = <SC_R_MIPI_1_PWM_0>;
+			pd_mipi_dsi1: PD_MIPI_1_DSI {
+				reg = <SC_R_MIPI_1>;
 				#power-domain-cells = <0>;
-				power-domains =<&pd_mipi_dsi1>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 {
+					reg = <SC_R_MIPI_1_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
+				pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 {
+					reg = <SC_R_MIPI_1_I2C_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
+				pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 {
+					reg = <SC_R_MIPI_1_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
 			};
 		};
 
-- 
2.17.1