From f78462d003a6e15f6f94991ea50ebf884eeb9205 Mon Sep 17 00:00:00 2001
From: Josep Orga <jorga@somdevices.com>
Date: Thu, 2 Sep 2021 09:22:41 +0200
Subject: [PATCH] imx8mm-somdevices: Add imx8mm-somdevices lpddr4
 configuration.

Signed-off-by: Josep Orga <jorga@somdevices.com>
---
 .../imx8mm_somdevices/lpddr4_timing.c         | 77 +++++++++----------
 1 file changed, 38 insertions(+), 39 deletions(-)

diff --git a/board/somdevices/imx8mm_somdevices/lpddr4_timing.c b/board/somdevices/imx8mm_somdevices/lpddr4_timing.c
index 3495b9c931..184d08fdef 100644
--- a/board/somdevices/imx8mm_somdevices/lpddr4_timing.c
+++ b/board/somdevices/imx8mm_somdevices/lpddr4_timing.c
@@ -1,22 +1,27 @@
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2019 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
  */
 
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
 
 struct dram_cfg_param ddr_ddrc_cfg[] = {
-	/* Initialize DDRC registers */
+	/** Initialize DDRC registers **/
 	{ 0x3d400304, 0x1 },
 	{ 0x3d400030, 0x1 },
 	{ 0x3d400000, 0xa1080020 },
-	{ 0x3d400020, 0x223 },
-	{ 0x3d400024, 0x16e3600 },
-	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d400020, 0x203 },
+	{ 0x3d400024, 0x3a980 },
+	{ 0x3d400064, 0x5b0087 },
 	{ 0x3d4000d0, 0xc00305ba },
 	{ 0x3d4000d4, 0x940000 },
 	{ 0x3d4000dc, 0xd4002d },
@@ -32,7 +37,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d40011c, 0x401 },
 	{ 0x3d400130, 0x20600 },
 	{ 0x3d400134, 0xc100002 },
-	{ 0x3d400138, 0xd8 },
+	{ 0x3d400138, 0x8d },
 	{ 0x3d400144, 0x96004b },
 	{ 0x3d400180, 0x2ee0017 },
 	{ 0x3d400184, 0x2605b8e },
@@ -45,7 +50,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4001a8, 0x80000000 },
 	{ 0x3d4001b0, 0x11 },
 	{ 0x3d4001c0, 0x1 },
-	{ 0x3d4001c4, 0x0 },
+	{ 0x3d4001c4, 0x1 },
 	{ 0x3d4000f4, 0xc99 },
 	{ 0x3d400108, 0x70e1617 },
 	{ 0x3d400200, 0x1f },
@@ -53,9 +58,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400210, 0x1f1f },
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
-	{ 0x3d400218, 0x7070707 },
-
-	/* performance setting */
+	{ 0x3d400218, 0xf070707 },
 	{ 0x3d400250, 0x29001701 },
 	{ 0x3d400254, 0x2c },
 	{ 0x3d40025c, 0x4000030 },
@@ -67,12 +70,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400498, 0x620096 },
 	{ 0x3d40049c, 0x1100e07 },
 	{ 0x3d4004a0, 0xc8012c },
-
-	/* P1: 400mts */
-	{ 0x3d402020, 0x21 },
-	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402020, 0x1 },
+	{ 0x3d402024, 0x7d00 },
 	{ 0x3d402050, 0x20d040 },
-	{ 0x3d402064, 0xc001c },
+	{ 0x3d402064, 0xc0012 },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
 	{ 0x3d4020e8, 0x66004d },
@@ -87,18 +88,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d40211c, 0x301 },
 	{ 0x3d402130, 0x20300 },
 	{ 0x3d402134, 0xa100002 },
-	{ 0x3d402138, 0x1d },
+	{ 0x3d402138, 0x13 },
 	{ 0x3d402144, 0x14000a },
 	{ 0x3d402180, 0x640004 },
 	{ 0x3d402190, 0x3818200 },
 	{ 0x3d402194, 0x80303 },
 	{ 0x3d4021b4, 0x100 },
-
-	/* p2: 100mts */
-	{ 0x3d403020, 0x21 },
-	{ 0x3d403024, 0xc3500 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1 },
+	{ 0x3d403024, 0x1f40 },
 	{ 0x3d403050, 0x20d040 },
-	{ 0x3d403064, 0x30007 },
+	{ 0x3d403064, 0x30005 },
 	{ 0x3d4030dc, 0x840000 },
 	{ 0x3d4030e0, 0x310000 },
 	{ 0x3d4030e8, 0x66004d },
@@ -113,14 +113,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d40311c, 0x301 },
 	{ 0x3d403130, 0x20300 },
 	{ 0x3d403134, 0xa100002 },
-	{ 0x3d403138, 0x8 },
+	{ 0x3d403138, 0x5 },
 	{ 0x3d403144, 0x50003 },
 	{ 0x3d403180, 0x190004 },
 	{ 0x3d403190, 0x3818200 },
 	{ 0x3d403194, 0x80303 },
 	{ 0x3d4031b4, 0x100 },
-
-	/* default boot point */
+	{ 0x3d4030f4, 0xc99 },
 	{ 0x3d400028, 0x0 },
 };
 
@@ -136,20 +135,20 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x100a7, 0x7 },
 	{ 0x110a0, 0x0 },
 	{ 0x110a1, 0x1 },
-	{ 0x110a2, 0x3 },
-	{ 0x110a3, 0x4 },
-	{ 0x110a4, 0x5 },
-	{ 0x110a5, 0x2 },
-	{ 0x110a6, 0x7 },
-	{ 0x110a7, 0x6 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
 	{ 0x120a0, 0x0 },
-	{ 0x120a1, 0x1 },
-	{ 0x120a2, 0x3 },
-	{ 0x120a3, 0x2 },
-	{ 0x120a4, 0x5 },
-	{ 0x120a5, 0x4 },
-	{ 0x120a6, 0x7 },
-	{ 0x120a7, 0x6 },
+	{ 0x120a1, 0x6 },
+	{ 0x120a2, 0x7 },
+	{ 0x120a3, 0x5 },
+	{ 0x120a4, 0x4 },
+	{ 0x120a5, 0x2 },
+	{ 0x120a6, 0x3 },
+	{ 0x120a7, 0x1 },
 	{ 0x130a0, 0x0 },
 	{ 0x130a1, 0x1 },
 	{ 0x130a2, 0x2 },
@@ -208,8 +207,8 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x220024, 0x1ab },
 	{ 0x2003a, 0x0 },
 	{ 0x20056, 0x3 },
-	{ 0x120056, 0xa },
-	{ 0x220056, 0xa },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
 	{ 0x1004d, 0xe00 },
 	{ 0x1014d, 0xe00 },
 	{ 0x1104d, 0xe00 },
-- 
2.17.1