From f507802aabd252c8d96594e55056e771ea3c3222 Mon Sep 17 00:00:00 2001 From: Viorel Suman Date: Fri, 18 Aug 2017 11:39:07 +0300 Subject: [PATCH] MLK-13975: ASoC: fsl: Make AMIX working for 8 channels and 96kHz rate Double the master and related clocks frequencies for AMIX SAIs in order to make AMIX working for 8 channels and 96k Hz rate. Signed-off-by: Viorel Suman Reviewed-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 3de49e60ba19..17838fc8ee4d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -159,7 +159,7 @@ <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QM_AUD_SAI_6_MCLK>; assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <24576000>, <24576000>, <24576000>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <49152000>, <49152000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; @@ -172,7 +172,7 @@ <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QM_AUD_SAI_7_MCLK>; assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <24576000>, <24576000>, <24576000>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <49152000>, <49152000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; -- 2.17.1