From f10b3af7e65d7cf1a2ade98333a8f46d6bcea76c Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Tue, 10 Jan 2023 18:27:48 +0100 Subject: [PATCH] =?utf8?q?arm64:=20dts:=20Change=20old=20I2C4=5FSCL=20pin:?= =?utf8?q?=20=09=C2=B7=20PMIC=20INT=20changed=20to=20SD1=5FSTROBE=5FGPIO2?= =?utf8?q?=5FIO11.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Josep Orga --- arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi index bc19efcd1447..151f16363530 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi @@ -295,8 +295,8 @@ reg = <0x25>; pinctrl-0 = <&pinctrl_pmic>; pinctrl-names = "default"; - interrupt-parent = <&gpio5>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; nxp,i2c-lt-enable; regulators { @@ -809,7 +809,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x141 + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x141 >; }; -- 2.17.1