From ed0e368f201af0c4d3c155782b43f073e7ab1ba1 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 5 May 2020 00:51:44 -0700 Subject: [PATCH] MLK-23574-51 mx6sx_val: Add iMX6SX validation boards support Porting the iMX6SX 17x17 DDR3/LPDDR2 (14x14) validation board and 19x19 DDR3/LPDDR2 validation board support from v2019.04 u-boot. Signed-off-by: Ye Li (cherry picked from commit 766189e6d95c272beb6048f722eca720057e747e) --- arch/arm/dts/Makefile | 7 + arch/arm/dts/imx6sx-14x14-val.dts | 1372 +++++++++++++++++ arch/arm/dts/imx6sx-17x17-val-ecspi.dts | 29 + arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts | 20 + arch/arm/dts/imx6sx-17x17-val.dts | 1317 ++++++++++++++++ arch/arm/dts/imx6sx-19x19-val-ecspi.dts | 29 + arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts | 20 + arch/arm/dts/imx6sx-19x19-val.dts | 1308 ++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 29 + board/freescale/mx6sx_17x17_val/Kconfig | 23 + board/freescale/mx6sx_17x17_val/Makefile | 6 + board/freescale/mx6sx_17x17_val/imximage.cfg | 122 ++ .../freescale/mx6sx_17x17_val/imximage_wp.cfg | 118 ++ .../mx6sx_14x14_lpddr2_val.cfg | 155 ++ .../mx6sx_17x17_val/mx6sx_17x17_val.c | 803 ++++++++++ board/freescale/mx6sx_17x17_val/plugin.S | 281 ++++ board/freescale/mx6sx_19x19_val/Kconfig | 23 + board/freescale/mx6sx_19x19_val/Makefile | 6 + board/freescale/mx6sx_19x19_val/imximage.cfg | 161 ++ .../mx6sx_19x19_val/imximage_lpddr2.cfg | 143 ++ .../mx6sx_19x19_val/mx6sx_19x19_val.c | 830 ++++++++++ board/freescale/mx6sx_19x19_val/plugin.S | 289 ++++ configs/mx6sx_14x14_lpddr2_val_defconfig | 78 + configs/mx6sx_14x14_lpddr2_val_nand_defconfig | 81 + .../mx6sx_14x14_lpddr2_val_plugin_defconfig | 79 + configs/mx6sx_17x17_val_defconfig | 77 + configs/mx6sx_17x17_val_eimnor_defconfig | 71 + configs/mx6sx_17x17_val_nand_defconfig | 80 + configs/mx6sx_17x17_val_plugin_defconfig | 78 + configs/mx6sx_17x17_val_qspi2_defconfig | 81 + configs/mx6sx_17x17_val_spinor_defconfig | 81 + configs/mx6sx_17x17wp_val_defconfig | 77 + configs/mx6sx_19x19_ddr3_val_defconfig | 77 + configs/mx6sx_19x19_ddr3_val_eimnor_defconfig | 70 + configs/mx6sx_19x19_ddr3_val_nand_defconfig | 80 + configs/mx6sx_19x19_ddr3_val_plugin_defconfig | 78 + configs/mx6sx_19x19_ddr3_val_qspi2_defconfig | 81 + configs/mx6sx_19x19_ddr3_val_spinor_defconfig | 81 + configs/mx6sx_19x19_lpddr2_val_defconfig | 78 + .../mx6sx_19x19_lpddr2_val_plugin_defconfig | 79 + .../mx6sx_19x19_lpddr2_val_qspi2_defconfig | 82 + include/configs/mx6sx_17x17_val.h | 34 + include/configs/mx6sx_19x19_val.h | 23 + include/configs/mx6sx_val.h | 275 ++++ 44 files changed, 8912 insertions(+) create mode 100644 arch/arm/dts/imx6sx-14x14-val.dts create mode 100644 arch/arm/dts/imx6sx-17x17-val-ecspi.dts create mode 100644 arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts create mode 100644 arch/arm/dts/imx6sx-17x17-val.dts create mode 100644 arch/arm/dts/imx6sx-19x19-val-ecspi.dts create mode 100644 arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts create mode 100644 arch/arm/dts/imx6sx-19x19-val.dts create mode 100644 board/freescale/mx6sx_17x17_val/Kconfig create mode 100644 board/freescale/mx6sx_17x17_val/Makefile create mode 100644 board/freescale/mx6sx_17x17_val/imximage.cfg create mode 100644 board/freescale/mx6sx_17x17_val/imximage_wp.cfg create mode 100644 board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg create mode 100644 board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c create mode 100644 board/freescale/mx6sx_17x17_val/plugin.S create mode 100644 board/freescale/mx6sx_19x19_val/Kconfig create mode 100644 board/freescale/mx6sx_19x19_val/Makefile create mode 100644 board/freescale/mx6sx_19x19_val/imximage.cfg create mode 100644 board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg create mode 100644 board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c create mode 100644 board/freescale/mx6sx_19x19_val/plugin.S create mode 100644 configs/mx6sx_14x14_lpddr2_val_defconfig create mode 100644 configs/mx6sx_14x14_lpddr2_val_nand_defconfig create mode 100644 configs/mx6sx_14x14_lpddr2_val_plugin_defconfig create mode 100644 configs/mx6sx_17x17_val_defconfig create mode 100644 configs/mx6sx_17x17_val_eimnor_defconfig create mode 100644 configs/mx6sx_17x17_val_nand_defconfig create mode 100644 configs/mx6sx_17x17_val_plugin_defconfig create mode 100644 configs/mx6sx_17x17_val_qspi2_defconfig create mode 100644 configs/mx6sx_17x17_val_spinor_defconfig create mode 100644 configs/mx6sx_17x17wp_val_defconfig create mode 100644 configs/mx6sx_19x19_ddr3_val_defconfig create mode 100644 configs/mx6sx_19x19_ddr3_val_eimnor_defconfig create mode 100644 configs/mx6sx_19x19_ddr3_val_nand_defconfig create mode 100644 configs/mx6sx_19x19_ddr3_val_plugin_defconfig create mode 100644 configs/mx6sx_19x19_ddr3_val_qspi2_defconfig create mode 100644 configs/mx6sx_19x19_ddr3_val_spinor_defconfig create mode 100644 configs/mx6sx_19x19_lpddr2_val_defconfig create mode 100644 configs/mx6sx_19x19_lpddr2_val_plugin_defconfig create mode 100644 configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig create mode 100644 include/configs/mx6sx_17x17_val.h create mode 100644 include/configs/mx6sx_19x19_val.h create mode 100644 include/configs/mx6sx_val.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8267ba34c7..32d6ea2119 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -740,6 +740,13 @@ dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb dtb-$(CONFIG_MX6SX) += \ + imx6sx-14x14-val.dtb \ + imx6sx-17x17-val.dtb \ + imx6sx-17x17-val-ecspi.dtb \ + imx6sx-17x17-val-gpmi-weim.dtb \ + imx6sx-19x19-val.dtb \ + imx6sx-19x19-val-ecspi.dtb \ + imx6sx-19x19-val-gpmi-weim.dtb \ imx6sx-sabreauto.dtb \ imx6sx-sdb.dtb \ imx6sx-sdb-emmc.dtb \ diff --git a/arch/arm/dts/imx6sx-14x14-val.dts b/arch/arm/dts/imx6sx-14x14-val.dts new file mode 100644 index 0000000000..25c924286b --- /dev/null +++ b/arch/arm/dts/imx6sx-14x14-val.dts @@ -0,0 +1,1372 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "i.MX6 SoloX 14x14 VAL Board"; + compatible = "fsl,imx6sx-14x14-lpddr2-val", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + off-on-delay-us = <20000>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-id = <1>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-id = <0>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_1>; + pinctrl-1 = <&pinctrl_i2c4_1_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4_3: usdhc4grp-3 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-17x17-val-ecspi.dts b/arch/arm/dts/imx6sx-17x17-val-ecspi.dts new file mode 100644 index 0000000000..36875a4aa9 --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-val-ecspi.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-17x17-val.dts" + +&usdhc3 { + status = "disabled"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "okay"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts b/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts new file mode 100644 index 0000000000..11568f441d --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-17x17-val.dts" + +&qspi2 { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/imx6sx-17x17-val.dts b/arch/arm/dts/imx6sx-17x17-val.dts new file mode 100644 index 0000000000..fe6750efbd --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-val.dts @@ -0,0 +1,1317 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "i.MX6 SoloX 17x17 VAL Board"; + compatible = "fsl,imx6sx-17x17-val", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + off-on-delay-us = <20000>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,wdog-reset = <1>; /* watchdog select of reset source */ + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_1>; + pinctrl-1 = <&pinctrl_i2c4_1_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + /* WDOG_B reset */ + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-19x19-val-ecspi.dts b/arch/arm/dts/imx6sx-19x19-val-ecspi.dts new file mode 100644 index 0000000000..fcbaf3526b --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-val-ecspi.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-val.dts" + +&usdhc3 { + status = "disabled"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "okay"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts b/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts new file mode 100644 index 0000000000..eb9738aff6 --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-val.dts" + +&qspi2 { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/imx6sx-19x19-val.dts b/arch/arm/dts/imx6sx-19x19-val.dts new file mode 100644 index 0000000000..76891b9ce9 --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-val.dts @@ -0,0 +1,1308 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "i.MX6 SoloX 19x19 VAL Board"; + compatible = "fsl,imx6sx-19x19-val", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&cs42888>; + }; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_1>; + status = "okay"; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_1>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 26 1>; + rst-gpios = <&gpio3 25 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_2>; + pinctrl-1 = <&pinctrl_i2c4_2_gpio>; + scl-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + cs42888: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>; + clock-names = "mclk"; + VA-supply = <®_3p3v>; + VD-supply = <®_3p3v>; + VLS-supply = <®_3p3v>; + VLC-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0 + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x1b0b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_1>; + status = "disabled"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + bus-width = <4>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x50000000 0x08000000>; + status = "disabled"; /* pin conflict with qspi, nand and lcd1 */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_2_gpio: i2c4grp-2-gpio { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x1b8b1 + MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x1b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 1be8e03f67..4d8d8ad84b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -484,6 +484,33 @@ config TARGET_MX6SXSABREAUTO select DM_THERMAL imply CMD_DM +config TARGET_MX6SX_14X14_VAL + bool "mx6sx_14x14_val" + depends on MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply CMD_DM + +config TARGET_MX6SX_17X17_VAL + bool "mx6sx_17x17_val" + depends on MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply CMD_DM + +config TARGET_MX6SX_19X19_VAL + bool "mx6sx_19x19_val" + depends on MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply CMD_DM + config TARGET_MX6UL_9X9_EVK bool "mx6ul_9x9_evk" depends on MX6UL @@ -812,6 +839,8 @@ source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sllevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" +source "board/freescale/mx6sx_17x17_val/Kconfig" +source "board/freescale/mx6sx_19x19_val/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" diff --git a/board/freescale/mx6sx_17x17_val/Kconfig b/board/freescale/mx6sx_17x17_val/Kconfig new file mode 100644 index 0000000000..07a3e7a5de --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SX_17X17_VAL || TARGET_MX6SX_14X14_VAL + +config SYS_BOARD + default "mx6sx_17x17_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sx_17x17_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config LPDDR2_BOARD + bool "Select for the board using LPDDR2 not default DDR3" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6sx_17x17_val/Makefile b/board/freescale/mx6sx_17x17_val/Makefile new file mode 100644 index 0000000000..b44bb36c4f --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sx_17x17_val.o diff --git a/board/freescale/mx6sx_17x17_val/imximage.cfg b/board/freescale/mx6sx_17x17_val/imximage.cfg new file mode 100644 index 0000000000..0718e230f3 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/imximage.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_17x17_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x00270025 +DATA 4 0x021b0810 0x001B001E +DATA 4 0x021b083c 0x4144013C +DATA 4 0x021b0840 0x01300128 +DATA 4 0x021b0848 0x4044464A +DATA 4 0x021b0850 0x3A383C34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_17x17_val/imximage_wp.cfg b/board/freescale/mx6sx_17x17_val/imximage_wp.cfg new file mode 100644 index 0000000000..a332840049 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/imximage_wp.cfg @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x002E003C +DATA 4 0x021b0810 0x001A003F +DATA 4 0x021b083c 0x41480150 +DATA 4 0x021b0840 0x012C0150 +DATA 4 0x021b0848 0x40404646 +DATA 4 0x021b0850 0x38363C32 +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg b/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg new file mode 100644 index 0000000000..beb7d2e906 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_17x17_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 +DATA 4 0x020e0340 0x00000028 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000028 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003028 +DATA 4 0x020e0334 0x00003028 +DATA 4 0x020e0338 0x00003028 +DATA 4 0x020e033c 0x00003028 + +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 + +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b082c 0x51111111 +DATA 4 0x021b0830 0x51111111 +DATA 4 0x021b0834 0x51111111 +DATA 4 0x021b0838 0x51111111 + +DATA 4 0x021b0848 0x42424244 + +DATA 4 0x021b0850 0x2E30322E +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 + +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x00008010 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x01038030 + +DATA 4 0x021b001c 0x00008018 +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x01038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 + +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c b/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c new file mode 100644 index 0000000000..3d1390cc0f --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c @@ -0,0 +1,803 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifndef CONFIG_MXC_SPI +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For validation board, silder the resistance */ + MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + SETUP_IOMUX_PADS(fec1_pads); +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /*always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /*always present */ + break; + } + + return ret; +} + +#ifdef CONFIG_MXC_SPI +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD3 (SDB) + * mmc1 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} + +#else +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD2 (SDA) + * mmc1 SD3 (SDB) + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_NAND_CE0_B__WEIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00610089, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x1c022000, WEIM_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_BASE_ADDR + 0x00c); + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 1 + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + +/* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(4, 22), "ar8031 reset"); + gpio_direction_output(IMX_GPIO_NR(4, 22) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(4, 22), 1); + +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus); + if (ret) { + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret); + return ret; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev); + if (ret) { + printf("MAX7322 Not found, ret = %d\n", ret); + return ret; + } + + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + ret = dm_i2c_write(dev, 0, &value, 1); + if (ret) { + printf("MAX7322 write failed, ret = %d\n", ret); + return ret; + } +#else + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(MAX7322_I2C_BUS); + + if (!i2c_probe(MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg_pads[] = { + /*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port >= 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x60, 0x38, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, + {"nand", MAKE_CFGVAL(0x80, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX6SX_14X14_VAL + puts("Board: MX6SX 14x14 VAL\n"); +#else + puts("Board: MX6SX 17x17 VAL\n"); +#endif + + return 0; +} diff --git a/board/freescale/mx6sx_17x17_val/plugin.S b/board/freescale/mx6sx_17x17_val/plugin.S new file mode 100644 index 0000000000..1b739b3fae --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/plugin.S @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_17x17_ddr3_evk_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00270025 + str r2, [r0, #0x80c] + ldr r2, =0x001B001E + str r2, [r0, #0x810] + ldr r2, =0x4144013C + str r2, [r0, #0x83c] + ldr r2, =0x01300128 + str r2, [r0, #0x840] + ldr r2, =0x4044464A + str r2, [r0, #0x848] + ldr r2, =0x3A383C34 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000005f + str r2, [r0, #0x040] + ldr r2, =0x84190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6sx_14x14_lpddr2_val_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000028 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + ldr r1, =0x00000028 + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00003028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00380000 + str r2, [r0, #0x890] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x51111111 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x42424244 + str r2, [r0, #0x848] + ldr r2, =0x2E30322E + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + ldr r2, =0x00020024 + str r2, [r0, #0x004] + ldr r2, =0x00100A42 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001748 + str r2, [r0, #0x018] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x02c] + ldr r2, =0x0000020e + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004f + str r2, [r0, #0x040] + ldr r2, =0xc3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003f8030 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x01038030 + str r2, [r0, #0x01c] + + ldr r2, =0x00008018 + str r2, [r0, #0x01c] + ldr r2, =0x003f8038 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x01038038 + str r2, [r0, #0x01c] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + ldr r2, =0x00000000 + str r2, [r0, #0x818] + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6_ddr_setting +#if defined(CONFIG_TARGET_MX6SX_14X14_VAL) && defined (CONFIG_LPDDR2_BOARD) + imx6sx_14x14_lpddr2_val_ddr_setting +#else + imx6sx_17x17_ddr3_evk_ddr_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sx_19x19_val/Kconfig b/board/freescale/mx6sx_19x19_val/Kconfig new file mode 100644 index 0000000000..2e3f14fc25 --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SX_19X19_VAL + +config SYS_BOARD + default "mx6sx_19x19_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sx_19x19_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config LPDDR2_BOARD + bool "Select for the board using LPDDR2 not default DDR3" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6sx_19x19_val/Makefile b/board/freescale/mx6sx_19x19_val/Makefile new file mode 100644 index 0000000000..eec06e97eb --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sx_19x19_val.o diff --git a/board/freescale/mx6sx_19x19_val/imximage.cfg b/board/freescale/mx6sx_19x19_val/imximage.cfg new file mode 100644 index 0000000000..a90fed967b --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/imximage.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* CLOCK */ +DATA 4 0x020e032c 0x00000030 + +/* ADDRESS */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 + +/* CONTROL */ +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +/* DATA STROBE */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 + +/* DATA */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4 0x021b0800 0xa1390003 +/* write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A + +DATA 4 0x021b08c0 0x2492244A + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init */ +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000 + +/* Initialize CS0: MT41K256M16HA-125 */ +/* MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg b/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg new file mode 100644 index 0000000000..9cd33360f4 --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 +DATA 4 0x020e0340 0x00000028 +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000028 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003028 +DATA 4 0x020e0334 0x00003028 +DATA 4 0x020e0338 0x00003028 +DATA 4 0x020e033c 0x00003028 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0x51111111 +DATA 4 0x021b0830 0x51111111 +DATA 4 0x021b0834 0x51111111 +DATA 4 0x021b0838 0x51111111 +DATA 4 0x021b0848 0x42424244 +DATA 4 0x021b0850 0x2E30322E +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x00008010 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x01038030 + +DATA 4 0x021b001c 0x00008018 +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x01038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c b/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c new file mode 100644 index 0000000000..15dbd2796b --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c @@ -0,0 +1,830 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* CABC enable */ + MX6_PAD_KEY_ROW1__GPIO2_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_lvds(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + enable_lvds_bridge(dev->bus); + + SETUP_IOMUX_PADS(lvds_ctrl_pads); + + /* Enable CABC */ + gpio_request(IMX_GPIO_NR(2, 16), "cabc enable"); + gpio_direction_output(IMX_GPIO_NR(2, 16) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 12), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 27), "lcd pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 12), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .enable = do_enable_lvds, + .detect = NULL, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .pixfmt = 24, + .addr = 0, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For arm2 board, silder the resistance */ + MX6_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + SETUP_IOMUX_PADS(fec1_pads); +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} +int board_mmc_init(struct bd_info *bis) +{ + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (SDA) + */ + SETUP_IOMUX_PADS(usdhc1_pads); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00010181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 1 + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + + /* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(6, 18), "ar8031 reset"); + gpio_direction_output(IMX_GPIO_NR(6, 18) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(6, 18), 1); + +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus); + if (ret) { + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret); + return ret; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev); + if (ret) { + printf("MAX7322 Not found, ret = %d\n", ret); + return ret; + } + + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + ret = dm_i2c_write(dev, 0, &value, 1); + if (ret) { + printf("MAX7322 write failed, ret = %d\n", ret); + return ret; + } +#else + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(MAX7322_I2C_BUS); + + if (!i2c_probe(MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port >= 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, + {"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6SX 19x19 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx6sx_19x19_val/plugin.S b/board/freescale/mx6sx_19x19_val/plugin.S new file mode 100644 index 0000000000..0e6b806624 --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/plugin.S @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_19x19_ddr3_val_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x002C003D + str r2, [r0, #0x80c] + ldr r2, =0x00110046 + str r2, [r0, #0x810] + ldr r2, =0x4160016C + str r2, [r0, #0x83c] + ldr r2, =0x013C016C + str r2, [r0, #0x840] + ldr r2, =0x46424446 + str r2, [r0, #0x848] + ldr r2, =0x3A3C3C3A + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000007f + str r2, [r0, #0x040] + ldr r2, =0x85190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00022227 + str r2, [r0, #0x818] + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm + +.macro imx6sx_19x19_lpddr2_val_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000028 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + ldr r1, =0x00000028 + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00003028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00380000 + str r2, [r0, #0x890] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x51111111 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x42424244 + str r2, [r0, #0x848] + ldr r2, =0x2E30322E + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + ldr r2, =0x00020024 + str r2, [r0, #0x004] + ldr r2, =0x00100A42 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001748 + str r2, [r0, #0x018] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x02c] + ldr r2, =0x0000020e + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004f + str r2, [r0, #0x040] + ldr r2, =0xc3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003f8030 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x01038030 + str r2, [r0, #0x01c] + + ldr r2, =0x00008018 + str r2, [r0, #0x01c] + ldr r2, =0x003f8038 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x01038038 + str r2, [r0, #0x01c] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + ldr r2, =0x00000000 + str r2, [r0, #0x818] + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_LPDDR2_BOARD) + imx6sx_19x19_lpddr2_val_ddr_setting +#else + imx6sx_19x19_ddr3_val_ddr_setting +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/configs/mx6sx_14x14_lpddr2_val_defconfig b/configs/mx6sx_14x14_lpddr2_val_defconfig new file mode 100644 index 0000000000..56fe7cee70 --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_14X14_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb" +CONFIG_LPDDR2_BOARD=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig new file mode 100644 index 0000000000..a6507e6e0f --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_14X14_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_NAND_BOOT=y +CONFIG_LPDDR2_BOARD=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig new file mode 100644 index 0000000000..f7a8461b90 --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_14X14_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb" +CONFIG_LPDDR2_BOARD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_defconfig b/configs/mx6sx_17x17_val_defconfig new file mode 100644 index 0000000000..e405019822 --- /dev/null +++ b/configs/mx6sx_17x17_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_eimnor_defconfig b/configs/mx6sx_17x17_val_eimnor_defconfig new file mode 100644 index 0000000000..0c213b53a0 --- /dev/null +++ b/configs/mx6sx_17x17_val_eimnor_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x501C0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_nand_defconfig b/configs/mx6sx_17x17_val_nand_defconfig new file mode 100644 index 0000000000..b0e50a12c4 --- /dev/null +++ b/configs/mx6sx_17x17_val_nand_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_plugin_defconfig b/configs/mx6sx_17x17_val_plugin_defconfig new file mode 100644 index 0000000000..e866b7b0c1 --- /dev/null +++ b/configs/mx6sx_17x17_val_plugin_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_qspi2_defconfig b/configs/mx6sx_17x17_val_qspi2_defconfig new file mode 100644 index 0000000000..b2fcf68f47 --- /dev/null +++ b/configs/mx6sx_17x17_val_qspi2_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_spinor_defconfig b/configs/mx6sx_17x17_val_spinor_defconfig new file mode 100644 index 0000000000..40f0454e5c --- /dev/null +++ b/configs/mx6sx_17x17_val_spinor_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17wp_val_defconfig b/configs/mx6sx_17x17wp_val_defconfig new file mode 100644 index 0000000000..b808df0bdc --- /dev/null +++ b/configs/mx6sx_17x17wp_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage_wp.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_defconfig b/configs/mx6sx_19x19_ddr3_val_defconfig new file mode 100644 index 0000000000..83b2519f1f --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig new file mode 100644 index 0000000000..555303df73 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_ADDR=0x500E0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_nand_defconfig b/configs/mx6sx_19x19_ddr3_val_nand_defconfig new file mode 100644 index 0000000000..5f65772900 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_nand_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig new file mode 100644 index 0000000000..19f1464d24 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig new file mode 100644 index 0000000000..e09a4bd06f --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig new file mode 100644 index 0000000000..ef14983977 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_val_defconfig b/configs/mx6sx_19x19_lpddr2_val_defconfig new file mode 100644 index 0000000000..ae93be649b --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig new file mode 100644 index 0000000000..f1b9c65a22 --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig new file mode 100644 index 0000000000..f75f59393c --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_QSPI_BOOT=y +CONFIG_LPDDR2_BOARD=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/include/configs/mx6sx_17x17_val.h b/include/configs/mx6sx_17x17_val.h new file mode 100644 index 0000000000..d9ab929044 --- /dev/null +++ b/include/configs/mx6sx_17x17_val.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_17X17_VAL_CONFIG_H +#define __MX6SX_17X17_VAL_CONFIG_H + +#include "mx6sx_val.h" + +#ifdef CONFIG_MXC_SPI /* Pin conflict between SPI-NOR and SD2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#else +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#endif + +#ifdef CONFIG_MXC_SPI +#undef CONFIG_SYS_FLASH_SECT_SIZE +#undef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#endif diff --git a/include/configs/mx6sx_19x19_val.h b/include/configs/mx6sx_19x19_val.h new file mode 100644 index 0000000000..7d2b820ad0 --- /dev/null +++ b/include/configs/mx6sx_19x19_val.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_19X19_VAL_CONFIG_H +#define __MX6SX_19X19_VAL_CONFIG_H + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_GIS +#endif + +#include "mx6sx_val.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#endif diff --git a/include/configs/mx6sx_val.h b/include/configs/mx6sx_val.h new file mode 100644 index 0000000000..b3416bc775 --- /dev/null +++ b/include/configs/mx6sx_val.h @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX VAL board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_VAL_CONFIG_H +#define __MX6SX_VAL_CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_DBG_MONITOR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHY_ATHEROS + +/* I2C configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#ifdef CONFIG_IMX_BOOTAUX +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 /* Set to QSPI2 B flash at default */ +#define SF_QSPI2_B_CS_NUM 2 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 /* Set to QSPI2 B flash at default */ +#define SF_QSPI2_B_CS_NUM 1 +#endif + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 1:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=Hannstar-XGA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "panel=Hannstar-XGA\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#ifdef CONFIG_NAND_MXS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#ifdef CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_CSI +#define CONFIG_VIDEO_PXP +#define CONFIG_VIDEO_VADC +#endif +#endif + + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#ifndef CONFIG_DM_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_FLAGS 0 +/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#endif /* __CONFIG_H */ -- 2.17.1