From e8a76c8fc2688ca8a5109234163894a06175e408 Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Thu, 9 Nov 2017 09:37:06 +0200 Subject: [PATCH] MLK-16918-13: arm64: dtsi: fsl-imx8mq: Add mipi-dsi-specific nodes Add support for mipi-dsi DRM driver in DTS files for i.MX8mq platform. Signed-off-by: Robert Chiras --- arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi | 63 ++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi index 00fc6ab37443..6eceeb47e672 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi @@ -40,6 +40,8 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + dsi_phy0 = &mipi_dsi_phy_drm; + mipi_dsi0 = &mipi_dsi_drm; }; cpus { @@ -502,7 +504,7 @@ mipi_dsi: mipi_dsi@30A00000 { compatible = "fsl,imx8mq-mipi-dsi"; - reg = <0x0 0x30a00000 0x0 0x10000>; /* DSI registers */ + reg = <0x0 0x30a00000 0x0 0x10000>; /* DSI registers */ interrupts = ; clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>, <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>, @@ -524,6 +526,65 @@ status = "disabled"; }; + mipi_dsi_phy_drm: dsi_phy_drm@30A00300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8mq-mipi-dsi-phy"; + reg = <0x0 0x30A00300 0x0 0x100>; + power-domains = <&mipi_pd>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge_drm: mipi_dsi_bridge_drm@30A00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x30A00000 0x0 0x400>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>, + <&clk IMX8MQ_CLK_DSI_AHB_DIV>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + clock-names = "phy_ref", "rx_esc", "tx_esc"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <80000000>; + power-domains = <&mipi_pd>; + phys = <&mipi_dsi_phy_drm>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + mipi_dsi_drm: mipi_dsi_drm@30A00000 { + compatible = "fsl,imx8mq-mipi-dsi_drm"; + clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>; + clock-names = "core", "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>, + <&clk IMX8MQ_CLK_DSI_CORE_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>; + assigned-clock-rates = <594000000>, <266000000>; + power-domains = <&mipi_pd>; + src = <&src>; + mux-sel = <&gpr>; + phys = <&mipi_dsi_phy_drm>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge_in>; + }; + }; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x0 0x30330000 0x0 0x10000>; -- 2.17.1