From e0cfcb2b44ba61b8a1a8f2b65a25f34831598ecf Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 5 May 2020 08:09:38 -0700 Subject: [PATCH] MLK-23574-53 mx6ul_val: Add iMX6UL validation boards support Porting the iMX6UL DDR3/LPDDR2 validation board support from v2019.04 u-boot. Signed-off-by: Ye Li (cherry picked from commit 1061ac589ce689246da25784bf960230b07b4e33) --- arch/arm/dts/Makefile | 4 + arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts | 23 + .../dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts | 34 + arch/arm/dts/imx6ul-14x14-ddr3-val.dts | 775 ++++++++++++ arch/arm/dts/imx6ul-14x14-lpddr2-val.dts | 779 ++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 22 + board/freescale/mx6ul_14x14_ddr3_val/Kconfig | 26 + board/freescale/mx6ul_14x14_ddr3_val/Makefile | 6 + .../mx6ul_14x14_ddr3_val/imximage.cfg | 115 ++ .../mx6ul_14x14_ddr3_val.c | 1066 +++++++++++++++++ board/freescale/mx6ul_14x14_ddr3_val/plugin.S | 135 +++ .../freescale/mx6ul_14x14_lpddr2_val/Kconfig | 24 + .../freescale/mx6ul_14x14_lpddr2_val/Makefile | 6 + .../mx6ul_14x14_lpddr2_val/imximage.cfg | 122 ++ .../mx6ul_14x14_lpddr2_val.c | 1022 ++++++++++++++++ .../freescale/mx6ul_14x14_lpddr2_val/plugin.S | 147 +++ configs/mx6ul_14x14_ddr3_val_defconfig | 75 ++ configs/mx6ul_14x14_ddr3_val_eimnor_defconfig | 62 + configs/mx6ul_14x14_ddr3_val_emmc_defconfig | 67 ++ configs/mx6ul_14x14_ddr3_val_nand_defconfig | 75 ++ configs/mx6ul_14x14_ddr3_val_plugin_defconfig | 76 ++ configs/mx6ul_14x14_ddr3_val_qspi1_defconfig | 77 ++ configs/mx6ul_14x14_ddr3_val_spinor_defconfig | 78 ++ configs/mx6ul_14x14_lpddr2_val_defconfig | 66 + .../mx6ul_14x14_lpddr2_val_eimnor_defconfig | 66 + include/configs/mx6ul_14x14_ddr3_val.h | 39 + include/configs/mx6ul_14x14_lpddr2_val.h | 49 + include/configs/mx6ul_val.h | 232 ++++ 28 files changed, 5268 insertions(+) create mode 100644 arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts create mode 100644 arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts create mode 100644 arch/arm/dts/imx6ul-14x14-ddr3-val.dts create mode 100644 arch/arm/dts/imx6ul-14x14-lpddr2-val.dts create mode 100644 board/freescale/mx6ul_14x14_ddr3_val/Kconfig create mode 100644 board/freescale/mx6ul_14x14_ddr3_val/Makefile create mode 100644 board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg create mode 100644 board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c create mode 100644 board/freescale/mx6ul_14x14_ddr3_val/plugin.S create mode 100644 board/freescale/mx6ul_14x14_lpddr2_val/Kconfig create mode 100644 board/freescale/mx6ul_14x14_lpddr2_val/Makefile create mode 100644 board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg create mode 100644 board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c create mode 100644 board/freescale/mx6ul_14x14_lpddr2_val/plugin.S create mode 100644 configs/mx6ul_14x14_ddr3_val_defconfig create mode 100644 configs/mx6ul_14x14_ddr3_val_eimnor_defconfig create mode 100644 configs/mx6ul_14x14_ddr3_val_emmc_defconfig create mode 100644 configs/mx6ul_14x14_ddr3_val_nand_defconfig create mode 100644 configs/mx6ul_14x14_ddr3_val_plugin_defconfig create mode 100644 configs/mx6ul_14x14_ddr3_val_qspi1_defconfig create mode 100644 configs/mx6ul_14x14_ddr3_val_spinor_defconfig create mode 100644 configs/mx6ul_14x14_lpddr2_val_defconfig create mode 100644 configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig create mode 100644 include/configs/mx6ul_14x14_ddr3_val.h create mode 100644 include/configs/mx6ul_14x14_lpddr2_val.h create mode 100644 include/configs/mx6ul_val.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cd32024984..a28e0bd4f9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -760,6 +760,10 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb \ + imx6ul-14x14-ddr3-val.dtb \ + imx6ul-14x14-ddr3-val-emmc.dtb \ + imx6ul-14x14-ddr3-val-gpmi-weim.dtb \ + imx6ul-14x14-lpddr2-val.dtb \ imx6ul-14x14-evk.dtb \ imx6ul-14x14-evk-emmc.dtb \ imx6ul-14x14-evk-gpmi-weim.dtb \ diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts new file mode 100644 index 0000000000..336f0a4e0c --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-val.dts" + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1_8bit>; + pinctrl-1 = <&pinctrl_usdhc1_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_8bit_200mhz>; + bus-width = <8>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + tuning-step = <2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts new file mode 100644 index 0000000000..fd5b550c9a --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-val.dts" + +/* + * solve pin conflict with NAND + * + * USDHC2_CD, SD2_RST_B, USDHC2_WP conflict with RAWNAND CE pins , also + * overwritten the conflict of SD2_RST_B with RAWNAND ALE in hog + * QSPI CLK, CE and DATA pins conflict with RAWNAND data pins and CE, CLE, RB, + * WP, DQS pin + * + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; +}; + +&qspi{ + status = "disabled"; +}; + +&gpmi{ + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val.dts new file mode 100644 index 0000000000..ded6a55496 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-val.dts @@ -0,0 +1,775 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "i.MX6 UltraLite DDR3 VAL Board"; + compatible = "fsl,imx6ul-14x14-ddr3-val", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "okay"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>; + + imx6ul-ddr3-val { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x17059 /* SD2 CD */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x17059 /* SD2 WP */ + >; + }; + + pinctrl_hog1: hoggrp1 { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESECT */ + >; + }; + + pinctrl_hog_sd: hoggrp_sd { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170f9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100f9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts b/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts new file mode 100644 index 0000000000..695cb10746 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts @@ -0,0 +1,779 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "i.MX6 UltraLite 14X14 LPDDR2 VAL Board"; + compatible = "fsl,imx6ul-14x14-lpddr2-val", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 22 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "disabled"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + keep-power-in-suspend; + vmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>; + + imx6ul-14x14-lpddr2-val { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_hog_nand: hoggrp_nand { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + >; + }; + + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0 + MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0 + MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088 + MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2_8bit_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9a22701326..5acd222101 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -541,6 +541,26 @@ config TARGET_MX6UL_14X14_EVK select OF_SYSTEM_SETUP imply CMD_DM +config TARGET_MX6UL_14X14_DDR3_VAL + bool "mx6ul_14x14_ddr3_val" + depends on MX6UL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP + imply CMD_DM + +config TARGET_MX6UL_14X14_LPDDR2_VAL + bool "mx6ul_14x14_lpddr2_val" + depends on MX6UL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP + imply CMD_DM + config TARGET_MX6UL_ENGICAM bool "Support Engicam GEAM6UL/Is.IoT" depends on MX6UL @@ -851,6 +871,8 @@ source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6sx_17x17_val/Kconfig" source "board/freescale/mx6sx_19x19_val/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/freescale/mx6ul_14x14_ddr3_val/Kconfig" +source "board/freescale/mx6ul_14x14_lpddr2_val/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" diff --git a/board/freescale/mx6ul_14x14_ddr3_val/Kconfig b/board/freescale/mx6ul_14x14_ddr3_val/Kconfig new file mode 100644 index 0000000000..2f057ef8c6 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/Kconfig @@ -0,0 +1,26 @@ +if TARGET_MX6UL_14X14_DDR3_VAL + +config SYS_BOARD + default "mx6ul_14x14_ddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_ddr3_val" + +config MX6UL_DDR3_VAL_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6UL_DDR3_VAL_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6ul_14x14_ddr3_val/Makefile b/board/freescale/mx6ul_14x14_ddr3_val/Makefile new file mode 100644 index 0000000000..e9f6edc422 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_ddr3_val.o diff --git a/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg b/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg new file mode 100644 index 0000000000..cd3372bd7a --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_ddr3_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x0013000F +DATA 4 0x021B083C 0x415D0159 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333000 +DATA 4 0x021B000C 0x676B54B3 +DATA 4 0x021B0010 0xB68E0A83 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00211740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0x85180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c b/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c new file mode 100644 index 0000000000..31076f6c3d --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c @@ -0,0 +1,1066 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC_IMX +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* + * The following 4 pins conflicts with qspi. + * You can comment out the following 4 pins and change + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4} + * to make emmc and qspi coexists. + */ + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#if !defined(CONFIG_CMD_NAND) +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_CSI_VSYNC__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_HSYNC__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6UL_DDR3_VAL_USDHC2_REWORK +#if defined(CONFIG_MTD_NOR_FLASH) || defined(CONFIG_MXC_SPI) +#error "Pin conflicts!" +#endif + /* conflict with eimnor/spinor */ + MX6_PAD_CSI_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + /* VSELECT */ + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* + * Pin conflicts with NAND ALE, if want to test nand, + * Connect R169(B), disconnect R169(A). + * + * RST_B + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +/* pin conflicts with eim nor */ +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1; +} +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +/* pin conflicts with nand usdhc2 lcd enet, ecspi */ +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_LCD_DATA08__EIM_DATA00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA09__EIM_DATA01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA10__EIM_DATA02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA11__EIM_DATA03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA12__EIM_DATA04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA13__EIM_DATA05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA14__EIM_DATA06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA15__EIM_DATA07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA16__EIM_DATA08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA17__EIM_DATA09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA18__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA19__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA20__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA21__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA22__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA23__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00010181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + if (check_module_fused(MODULE_EIM)) { + printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR); + return; + } + + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} + +int board_flash_wp_on(void) +{ + if (check_module_fused(MODULE_EIM)) + return 1; /* Skip flash init */ + + return 0; +} + +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + /* Pin conflicts with LCD PWM1 */ + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK + /* If want to use qspi, should change to 4 bit width */ + {USDHC1_BASE_ADDR, 0, 8}, +#else + {USDHC1_BASE_ADDR, 0, 4}, +#endif +#if !defined(CONFIG_CMD_NAND) + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC1_CD_GPIO); +#endif + break; +#if !defined(CONFIG_CMD_NAND) + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; +#endif + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK + SETUP_IOMUX_PADS(usdhc1_emmc_pads); +#else + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); +#endif + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + /* 3.3V */ + gpio_request(USDHC1_VSELECT, "usdhc1 vsel"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_VSELECT, 0); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */ +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MODULE_ENET1)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + + } else { + if (check_module_fused(MODULE_ENET2)) + return -1; + + /* clk from phy, set gpr1[14], clear gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + static struct pmic *pfuze; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + * + * Here we can not set this, since SD1_RST_B conflicts with GWDOG. + * We use SD1, so will not set WDOG pads, also GWDOG default is + * DNP. + */ + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14X14 DDR3 Validation\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_ddr3_val/plugin.S b/board/freescale/mx6ul_14x14_ddr3_val/plugin.S new file mode 100644 index 0000000000..06b939fc24 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/plugin.S @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0013000F + str r1, [r0, #0x80C] + ldr r1, =0x415D0159 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333000 + str r1, [r0, #0x008] + ldr r1, =0x676B54B3 + str r1, [r0, #0x00C] + ldr r1, =0xB68E0A83 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00211740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0x85180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + str r1, [r0, #0x84] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_ddr3_val_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig b/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig new file mode 100644 index 0000000000..28c4515b73 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MX6UL_14X14_LPDDR2_VAL + +config SYS_BOARD + default "mx6ul_14x14_lpddr2_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_lpddr2_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6UL_LPDDR2_VAL_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. + +endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/Makefile b/board/freescale/mx6ul_14x14_lpddr2_val/Makefile new file mode 100644 index 0000000000..e056bae157 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_lpddr2_val.o diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg b/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg new file mode 100644 index 0000000000..ae47a81ee1 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_lpddr2_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000028 +DATA 4 0x020E0250 0x00000028 +DATA 4 0x020E024C 0x00000028 +DATA 4 0x020E0490 0x00000028 +DATA 4 0x020E0288 0x00000028 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000028 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003028 +DATA 4 0x020E0284 0x00003028 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000028 +DATA 4 0x020E04A4 0x00000028 +DATA 4 0x020E0244 0x00000028 +DATA 4 0x020E0248 0x00000028 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x00470000 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020012 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00001748 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x0F9F0682 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025576 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c b/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c new file mode 100644 index 0000000000..d94d14f113 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c @@ -0,0 +1,1022 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +#if !defined(CONFIG_CMD_NAND) + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + + MX6_PAD_CSI_DATA04__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#if !defined(CONFIG_CMD_NAND) + +#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +/* pin conflicts with eim nor */ +static iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 22), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 22), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 22)) : -1; +} +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +/* pin conflicts with ECSIP2, USDHC1, USDCH2, NAND, SIM, ENET2 */ +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_HSYNC__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WP_B__EIM_BCLK | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00610089, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x1c022000, WEIM_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_BASE_ADDR + 0x00c); + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* Conflict with UART1 */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +#if !defined(CONFIG_CMD_NAND) +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 1}, + {USDHC2_BASE_ADDR, 0, 8}, +}; +#else +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; +#endif + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 26) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(4, 11) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; +#if !defined(CONFIG_CMD_NAND) + case USDHC2_BASE_ADDR: +#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK + ret = !gpio_get_value(USDHC2_CD_GPIO); +#else + ret = 1; +#endif + break; +#endif + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) + case 1: +#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#else + SETUP_IOMUX_PADS(usdhc2_emmc_pads); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#endif + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d)" + " than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(4, 16), "backlight"); + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (1 == fec_id) { + if (check_module_fused(MODULE_ENET2)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + } else { + if (check_module_fused(MODULE_ENET1)) + return -1; + + /* clk from phy, set gpr1[13], clear gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 1.3V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 1.3V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + /* + * This function should be invoked after setup_fec, + * because ENET2_RX_ER conflicts. However, we rarely need + * ENET2_RX_ER for enet, and when use eimnor, we do not + * have sd1/sd2, enet is a must to boot kernel and nfsrootfs. + */ + setup_eimnor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14X14 LPDDR2 Validation\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S b/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S new file mode 100644 index 0000000000..6ef2013eec --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_lpddr2_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000028 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000028 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003028 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000028 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x5C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + str r1, [r0, #0x84] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_lpddr2_val_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/configs/mx6ul_14x14_ddr3_val_defconfig b/configs/mx6ul_14x14_ddr3_val_defconfig new file mode 100644 index 0000000000..bb97f951a0 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig new file mode 100644 index 0000000000..58bd8fb80e --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x501C0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NET=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=n diff --git a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig new file mode 100644 index 0000000000..2e33849ce2 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val-emmc" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_nand_defconfig b/configs/mx6ul_14x14_ddr3_val_nand_defconfig new file mode 100644 index 0000000000..5269f33b9f --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_nand_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val-gpmi-weim" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig new file mode 100644 index 0000000000..f4b80019b2 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig new file mode 100644 index 0000000000..74a3cfe7bb --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig new file mode 100644 index 0000000000..3bc6c44cc0 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_SPI_BOOT=y +CONFIG_MXC_SPI=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_lpddr2_val_defconfig b/configs/mx6ul_14x14_lpddr2_val_defconfig new file mode 100644 index 0000000000..f052176d1b --- /dev/null +++ b/configs/mx6ul_14x14_lpddr2_val_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_LPDDR2_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig new file mode 100644 index 0000000000..92da102b94 --- /dev/null +++ b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_LPDDR2_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x501C0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/include/configs/mx6ul_14x14_ddr3_val.h b/include/configs/mx6ul_14x14_ddr3_val.h new file mode 100644 index 0000000000..9aa8cd68a8 --- /dev/null +++ b/include/configs/mx6ul_14x14_ddr3_val.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_DDR3_VAL_CONFIG_H +#define __MX6UL_14X14_DDR3_VAL_CONFIG_H + + +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_val.h" + +#define PHYS_SDRAM_SIZE SZ_1G + + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#endif diff --git a/include/configs/mx6ul_14x14_lpddr2_val.h b/include/configs/mx6ul_14x14_lpddr2_val.h new file mode 100644 index 0000000000..3cda6a72fd --- /dev/null +++ b/include/configs/mx6ul_14x14_lpddr2_val.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 LPDDR2 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_LPDDR2_VAL_CONFIG_H +#define __MX6UL_14X14_LPDDR2_VAL_CONFIG_H + +#ifdef CONFIG_MTD_NOR_FLASH +/* + * Conflicts with SD1/SD2/VIDEO/ENET + * ENET is keeped, since only RXER conflicts. + * If removed ENET, we can not boot kernel, since sd1/sd2 is disabled + * when support weimnor. + */ +#undef CONFIG_FSL_USDHC +#undef CONFIG_VIDEO +#endif + +#define BOOTARGS_CMA_SIZE "cma=96M " + +#include "mx6ul_val.h" + +#define PHYS_SDRAM_SIZE SZ_256M + + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 1 /* The ENET1 has pin conflict with UART1 */ + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#endif diff --git a/include/configs/mx6ul_val.h b/include/configs/mx6ul_val.h new file mode 100644 index 0000000000..f218528159 --- /dev/null +++ b/include/configs/mx6ul_val.h @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL ARM2 common. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_VAL_CONFIG_H +#define __MX6UL_VAL_CONFIG_H + + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND stuff */ +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#endif -- 2.17.1