From dd1cd4e998ccbfb552f0f4e3ea1736a444652406 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 27 Jul 2017 15:58:27 +0800 Subject: [PATCH] MLK-16052-2 PCI: imx: fix the pcieb link down issue The calibration value of PCIEA is mandatory required by PCIEB on iMX8QM. The RSTs of the PCIEA would be cleared when the PDs of PCIEA are turned off. The calibration value of PCIEA would be lost when the RSTs of PCIEA are cleared. So, the RSTs of PCIEA should be asserted when enable the PCIEB port. Otherwise, PCIEB wouldn't be functional. Signed-off-by: Richard Zhu --- drivers/pci/host/pci-imx6.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 936ec78a7e59..edd250b12ef8 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -376,6 +376,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { struct pcie_port *pp = &imx6_pcie->pp; u32 val, gpr1, gpr12; + int i; switch (imx6_pcie->variant) { case IMX6SX: @@ -432,19 +433,21 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), BIT(2)); break; case IMX8QM: - val = IMX8QM_CSR_PCIEA_OFFSET + imx6_pcie->ctrl_id * SZ_64K; - regmap_update_bits(imx6_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_BUTTON_RST_N, - IMX8QM_CTRL_BUTTON_RST_N); - regmap_update_bits(imx6_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_PERST_N, - IMX8QM_CTRL_PERST_N); - regmap_update_bits(imx6_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_POWER_UP_RST_N, - IMX8QM_CTRL_POWER_UP_RST_N); + for (i = 0; i <= imx6_pcie->ctrl_id; i++) { + val = IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + } break; case IMX8MQ: if (imx6_pcie->ctrl_id == 0) -- 2.17.1