From db06d0c7eba4d9d8c5fa3a95166f19d6247e1aab Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Fri, 13 Aug 2021 11:35:51 +0200 Subject: [PATCH] =?utf8?q?arm64:=20dts:=20imx8mm-somdevices.dtsi:=20Disabl?= =?utf8?q?ed=20not=20used=20peripherals:=20=09=C2=B7=20Disabled=20mipi=5Fc?= =?utf8?q?si=20and=20pcie.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Josep Orga --- .../boot/dts/freescale/imx8mm-somdevices.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi index ba2e998f9e9d..64a9b6f023b7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi @@ -130,7 +130,7 @@ &csi1_bridge { fsl,mipi-mode; - status = "okay"; + status = "disabled"; port { csi1_ep: endpoint { remote-endpoint = <&csi1_mipi_ep>; @@ -300,16 +300,16 @@ ov5640_mipi: ov5640_mipi@3c { compatible = "ovti,ov5640_mipi"; reg = <0x3c>; - status = "okay"; + status = "disabled"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + pinctrl-0 = <&pinctrl_csi>; clocks = <&clk IMX8MM_CLK_CLKO1>; clock-names = "csi_mclk"; assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; assigned-clock-parents = <&clk IMX8MM_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; - pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + //pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; mclk = <24000000>; mclk_source = <0>; port { @@ -327,7 +327,7 @@ &mipi_csi_1 { #address-cells = <1>; #size-cells = <0>; - status = "okay"; + status = "disabled"; port { mipi1_sensor_ep: endpoint@1 { remote-endpoint = <&ov5640_mipi1_ep>; @@ -371,7 +371,7 @@ <&clk IMX8MM_SYS_PLL2_100M>, <&clk IMX8MM_SYS_PLL2_250M>; ext_osc = <1>; - status = "okay"; + status = "disabled"; }; &pcie0_ep{ @@ -542,14 +542,9 @@ }; &iomuxc { - pinctrl_csi_pwn: csi_pwn_grp { + pinctrl_csi: csi_grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - pinctrl_csi_rst: csi_rst_grp { - fsl,pins = < MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 >; -- 2.17.1