From d06f256459f3458948f91a7aef2123ea9840eb36 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Mon, 3 Jul 2017 18:09:19 +0800 Subject: [PATCH] MLK-15313-2 ARM64: dts: imx8qm-lpddr4-arm2: add SD3.0 support Add SD3.0 support for USDHC2. Signed-off-by: Haibo Chen --- .../dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 52 +++++++++++++++++-- arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 2 + 2 files changed, 50 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 6a3af26d8ec4..67ed211694ed 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -82,6 +82,16 @@ enable-active-high; vin-supply = <®_can_en>; }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; sound-cs42888 { @@ -283,6 +293,14 @@ >; }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 @@ -291,8 +309,31 @@ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 - SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000045 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000025 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000025 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000025 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000025 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000025 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000047 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000027 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000027 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000027 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000027 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000027 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; @@ -383,11 +424,14 @@ }; &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index fa61319c015c..813f970c1a77 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -2000,6 +2000,8 @@ clock-names = "ipg", "per", "ahb"; assigned-clock-rates = <400000000>, <200000000>, <0>; power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; -- 2.17.1