From ce01e31261249df29d2bec49324c9231709fdc49 Mon Sep 17 00:00:00 2001 From: Teo Hall Date: Thu, 6 Feb 2020 11:10:12 -0600 Subject: [PATCH] MLK-23280: Add i.MX8DXL EVK Board support Add device trees, configs and board files for the i.MX8DXL EVK board. Signed-off-by: Ye Li Signed-off-by: Teo Hall (cherry picked from commit f0238679d332f1af2148d467804a93de8f868bd5) (cherry picked from commit 2ce08b29516a582b295f22565695e57da75e551f) --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi | 207 ++ arch/arm/dts/fsl-imx8dxl-evk.dts | 543 +++++ arch/arm/dts/fsl-imx8dxl.dtsi | 1907 +++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/freescale/imx8dxl_evk/Kconfig | 14 + board/freescale/imx8dxl_evk/Makefile | 8 + board/freescale/imx8dxl_evk/imx8dxl_evk.c | 171 ++ board/freescale/imx8dxl_evk/imximage.cfg | 22 + board/freescale/imx8dxl_evk/spl.c | 66 + .../freescale/imx8dxl_evk/uboot-container.cfg | 13 + configs/imx8dxl_evk_defconfig | 158 ++ include/configs/imx8dxl_evk.h | 305 +++ 13 files changed, 3421 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8dxl-evk.dts create mode 100644 arch/arm/dts/fsl-imx8dxl.dtsi create mode 100644 board/freescale/imx8dxl_evk/Kconfig create mode 100644 board/freescale/imx8dxl_evk/Makefile create mode 100644 board/freescale/imx8dxl_evk/imx8dxl_evk.c create mode 100644 board/freescale/imx8dxl_evk/imximage.cfg create mode 100644 board/freescale/imx8dxl_evk/spl.c create mode 100644 board/freescale/imx8dxl_evk/uboot-container.cfg create mode 100644 configs/imx8dxl_evk_defconfig create mode 100644 include/configs/imx8dxl_evk.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d7ed07296e..d1cf8a3bce 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -805,6 +805,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-mek.dtb \ fsl-imx8dx-mek.dtb \ fsl-imx8dxl-phantom-mek.dtb \ + fsl-imx8dxl-evk.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb diff --git a/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi new file mode 100644 index 0000000000..3f0b5a9b93 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; +}; + +&{/imx8dxl-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usb_otg1_vbus { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8dxl-evk} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + phy-mode = "rgmii-id"; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-evk.dts b/arch/arm/dts/fsl-imx8dxl-evk.dts new file mode 100644 index 0000000000..2e4aaff30f --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-evk.dts @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "fsl-imx8dxl.dtsi" + +/ { + model = "NXP i.MX8DXL EVK Board"; + compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec1: regfec1 { + compatible = "regulator-fixed"; + regulator-name = "fec1_supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&pca6416_a 11 GPIO_ACTIVE_LOW>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + u-boot,off-on-delay-us = <12000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca6416_a 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + + }; + + pcie_clk_sel_ext: fixedregulator@101 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <0000000>; + regulator-max-microvolt = <3300000>; + regulator-name = "clk_ext_sel"; + gpio = <&pca6416_a 10 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8dxl-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + SC_P_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + SC_P_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000021 /* RESET_B */ + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9646"; + reg = <0x70>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + v2x_i2c2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + audio_codec1_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + audio_codec2_i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + audio_codec3_i2c2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + m2_i2c2: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + pcie_i2c2: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + lcd_i2c2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; + + pca6416_a: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_b: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9646"; + reg = <0x70>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + alt_audio_codec1_i2c3: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + alt_audio_codec2_i2c3: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + alt_audio_codec3_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + usb1_i2c3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + usb2_i2c3: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; + + pca6416_c: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + phy-reset-gpios = <&pca6416_a 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + }; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + power-on-gpio = <&pca6416_a 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + enable-gpios = <&pca6416_a 10 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + phy-supply = <®_fec1>; + status = "disable"; + phy-reset-gpios = <&pca6416_a 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + /* mdio/mdc pins conflict with eqos, so should be shared mii bus + * fec1 pins has conflict with usdhc2 + * for bringup, only enable one mac + */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; /* ensure your net card phy id: 0x1 */ + }; + + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8dxl.dtsi b/arch/arm/dts/fsl-imx8dxl.dtsi new file mode 100644 index 0000000000..c65ad6052b --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl.dtsi @@ -0,0 +1,1907 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include "fsl-imx8-ca35.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "NXP i.MX8DXL"; + compatible = "fsl,imx8dxl"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &flexspi0; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usbotg2; + usbphy1 = &usbphy2; + pci0 = &pcieb; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10000>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <5000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10033>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <2300>; + min-residency-us = <14000>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + + mu: mu@5d1c0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1c0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + status = "okay"; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + imx8dxl-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu5a: PD_LSIO_MU5A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu8a: PD_LSIO_MU8A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <169>; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usbotg0>; + wakeup-irq = <169>; + }; + + }; + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <166>; + + pd_conn_usbotg1_phy: PD_CONN_USB_1_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usbotg1>; + wakeup-irq = <166>; + }; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <258>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + fsl,wakeup_irq = <262>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = ; + power-domains =<&pd_audio>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = ; + power-domains =<&pd_audio_pll0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = ; + power-domains =<&pd_audio_pll1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_ASRC_0_RXA { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_ASRC_0_RXB { + reg = ; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan2: PD_ASRC_0_RXC { + reg = ; + power-domains =<&pd_dma0_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan3: PD_ASRC_0_TXA { + reg = ; + power-domains =<&pd_dma0_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan4: PD_ASRC_0_TXB { + reg = ; + power-domains =<&pd_dma0_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan5: PD_ASRC_0_TXC { + reg = ; + power-domains =<&pd_dma0_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan5>; + }; + }; + }; + }; + }; + }; + }; + + pd_dma0_chan8: PD_SPDIF_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan9: PD_SPDIF_0_TX { + reg = ; + power-domains =<&pd_dma0_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_spdif0: PD_AUD_SPDIF_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan9>; + + }; + }; + }; + pd_dma0_chan12: PD_SAI_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan13: PD_SAI_0_TX { + reg = ; + power-domains =<&pd_dma0_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai0:PD_AUD_SAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan13>; + }; + }; + + }; + pd_dma0_chan14: PD_SAI_1_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan15: PD_SAI_1_TX { + reg = ; + power-domains =<&pd_dma0_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai1: PD_AUD_SAI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan15>; + }; + }; + }; + pd_dma0_chan16: PD_SAI_2_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai2: PD_AUD_SAI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan16>; + }; + }; + pd_dma0_chan17: PD_SAI_3_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai3: PD_AUD_SAI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan17>; + }; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + }; + }; + }; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_elcdif_pll>; + }; + }; + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <235>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <236>; + }; + + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <237>; + }; + }; + + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <345>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <346>; + + pd_dma2_chan10: PD_UART1_RX { + reg = ; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan11: PD_UART1_TX { + reg = ; + power-domains =<&pd_dma2_chan10>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma2_chan12: PD_UART2_RX { + reg = ; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = ; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <348>; + + pd_dma3_chan14: PD_UART3_RX { + reg = ; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan15: PD_UART3_TX { + reg = ; + power-domains =<&pd_dma3_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_pwm0: PD_DMA_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + + pd_hsio: hsio-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hsio_gpio: PD_HSIO_GPIO { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio_gpio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: PD_HSIO_PCIE_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + status = "disabled"; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QXP_CM40_I2C_CLK>, + <&clk IMX8QXP_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x5a180000 0x0 0x10000>; + clocks = <&clk IMX8QXP_LCD_CLK>, + <&clk IMX8QXP_LCD_PXL_CLK>, + <&clk IMX8QXP_LCD_IPG_CLK>; + clock-names = "pix", "disp_axi", "axi"; + assigned-clocks = <&clk IMX8QXP_LCD_SEL>, + <&clk IMX8QXP_LCD_PXL_SEL>, + <&clk IMX8QXP_ELCDIF_PLL_DIV>; + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>, + <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; + assigned-clock-rates = <0>, <24000000>, <804000000>; + interrupts = ; + power-domains = <&pd_dma_lcd0>; + status = "disabled"; + }; + + pwm_adma_lcdif: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5a190000 0 0x1000>; + clocks = <&clk IMX8QXP_PWM_IPG_CLK>, + <&clk IMX8QXP_PWM_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_dma_pwm0>; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_5: i2c-rpbus-5 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_12: i2c-rpbus-12 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_13: i2c-rpbus-13 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_14: i2c-rpbus-14 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_15: i2c-rpbus-15 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_ADC0_CLK>, + <&clk IMX8QXP_ADC0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_ADC0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_adc0>; + status = "disabled"; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C0_CLK>, + <&clk IMX8QXP_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C1_CLK>, + <&clk IMX8QXP_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C2_CLK>, + <&clk IMX8QXP_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C3_CLK>, + <&clk IMX8QXP_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x1000>; + clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbphy2: usbphy@0x5b110000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b110000 0x0 0x1000>; + clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg1_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + status = "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0e0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + fsl,usbphy = <&usbphy2>; + clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg1>; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan1>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan2>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x0 0x5b810000 0x0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8QXP_APBHDMA_CLK>; + power-domains = <&pd_conn_nand>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, + <&clk IMX8QXP_GPMI_APB_CLK>, + <&clk IMX8QXP_GPMI_BCH_CLK>, + <&clk IMX8QXP_GPMI_APB_BCH_CLK>, + <&clk IMX8QXP_APBHDMA_CLK>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd_conn_nand>; + assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; + + wu: wu { + compatible = "fsl,imx8-wu"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI0_CLK>, + <&clk IMX8QXP_SPI0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; + assigned-clock-rates = <20000000>; + power-domains = <&pd_dma_lpspi0>; + status = "disabled"; + }; + + lpspi2: lpspi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a020000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI2_CLK>, + <&clk IMX8QXP_SPI2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; + assigned-clock-rates = <20000000>; + power-domains = <&pd_dma_lpspi2>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART1_CLK>, + <&clk IMX8QXP_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan11>; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan13>; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART3_CLK>, + <&clk IMX8QXP_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma3_chan15>; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; + status = "disabled"; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ + <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ + <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ + <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + status = "okay"; + }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <16>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt0 */ + "edma0-chan23-rx"; /* gpt2 */ + status = "okay"; + }; + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_0_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59060000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_2_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + status = "disabled"; + power-domains = <&pd_sai2>; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59070000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_3_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + status = "disabled"; + power-domains = <&pd_sai3>; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_MQS_IPG>, + <&clk IMX8QXP_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-rates = <0>, <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, + <&clk IMX8QXP_SDHC1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, + <&clk IMX8QXP_SDHC2_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, + <&clk IMX8QXP_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet0>; + status = "disabled"; + }; + + eqos: ethernet@5b050000 { + compatible = "fsl,imx-eqos"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = , + ; + clocks = <&clk IMX8DXL_EQOS_ACLK>, <&clk IMX8DXL_EQOS_CSR_CLK>, <&clk IMX8DXL_EQOS_CLK>, + <&clk IMX8DXL_EQOS_PTP_CLK>; + clock-names = "aclk", "csr", "tx_clk", "ptp"; + assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>; + assigned-clock-rates = <125000000>; + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; + + gpt0: gpt0@5d140000 { + compatible = "fsl,imx8qxp-gpt"; + reg = <0x0 0x5d140000 0x0 0x4000>; + interrupts = ; + clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>; + clock-names = "ipg", "per"; + power-domains = <&pd_lsio_gpt0>; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QXP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8dxl-fspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, + <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>; + assigned-clock-rates = <29000000>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + ocotp: ocotp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8qxp-ocotp", "syscon"; + }; + + pcieb: pcie@0x5f010000 { + /* + * pcieb phyx1 lane1 in default, adjust it refer to the + * exact hw design. + */ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, + <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, + <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu_rpmsg: mu_rpmsg@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x5d200000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu5a>; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + status = "disabled"; + mub-partition = <3>; + power-domains = <&pd_lsio_mu5a>; + memory-region = <&rpmsg_dma_reserved>; + }; + }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x10000>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + + wdog: wdog { + compatible = "fsl,imx8-wdt"; + }; +}; + +&A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 900000 0 + >; + clocks = <&clk IMX8QXP_A35_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index f918537274..6a035b3287 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -114,11 +114,17 @@ config TARGET_IMX8DX_MEK select SUPPORT_SPL select IMX8QXP +config TARGET_IMX8DXL_EVK + bool "Support i.MX8DXL EVK board" + select BOARD_LATE_INIT + select IMX8DXL + endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/freescale/imx8dxl_phantom_mek/Kconfig" +source "board/freescale/imx8dxl_evk/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/board/freescale/imx8dxl_evk/Kconfig b/board/freescale/imx8dxl_evk/Kconfig new file mode 100644 index 0000000000..4162f326ff --- /dev/null +++ b/board/freescale/imx8dxl_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8DXL_EVK + +config SYS_BOARD + default "imx8dxl_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8dxl_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8dxl_evk/Makefile b/board/freescale/imx8dxl_evk/Makefile new file mode 100644 index 0000000000..f031c5fb50 --- /dev/null +++ b/board/freescale/imx8dxl_evk/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8dxl_evk.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8dxl_evk/imx8dxl_evk.c b/board/freescale/imx8dxl_evk/imx8dxl_evk.c new file mode 100644 index 0000000000..756ae189e4 --- /dev/null +++ b/board/freescale/imx8dxl_evk/imx8dxl_evk.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +static void board_gpio_init(void) +{ +} +#else +static inline void board_gpio_init(void) {} +#endif + +int checkboard(void) +{ + puts("Board: iMX8DXL EVK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +#ifdef CONFIG_DWC_ETH_QOS +static int setup_eqos(void) +{ + sc_err_t err; + + /* set GPR14:12 to b'001: RGMII mode */ + err = sc_misc_set_control(-1, SC_R_ENET_1, SC_C_INTF_SEL, 0x1); + if (err != SC_ERR_NONE) + printf("SC_R_ENET_1 INTF_SEL failed! (error = %d)\n", err); + + /* enable GPR11: CLK_GEN_EN */ + err = sc_misc_set_control(-1, SC_R_ENET_1, SC_C_CLK_GEN_EN, 1); + if (err != SC_ERR_NONE) + printf("SC_R_ENET_1 CLK_GEN_EN failed! (error = %d)\n", err); + + return 0; +} +#endif + +int board_init(void) +{ + board_gpio_init(); +#ifdef CONFIG_DWC_ETH_QOS + /* clock, phy interface mode */ + setup_eqos(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + }; + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_late_init(void) +{ + char *fdt_file; + bool m4_booted; + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8DXL"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + fdt_file = env_get("fdt_file"); + m4_booted = m4_parts_booted(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { + if (m4_booted) + env_set("fdt_file", "imx8dxl-evk-rpmsg.dtb"); + else + env_set("fdt_file", "imx8dxl-evk.dtb"); + } + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8dxl_evk/imximage.cfg b/board/freescale/imx8dxl_evk/imximage.cfg new file mode 100644 index 0000000000..e5f2a9e817 --- /dev/null +++ b/board/freescale/imx8dxl_evk/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8DXL */ +SOC_TYPE IMX8DXL +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8dxl-evk-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8dxl_evk/spl.c b/board/freescale/imx8dxl_evk/spl.c new file mode 100644 index 0000000000..f284b3f56e --- /dev/null +++ b/board/freescale/imx8dxl_evk/spl.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + board_quiesce_devices(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8dxl_evk/uboot-container.cfg b/board/freescale/imx8dxl_evk/uboot-container.cfg new file mode 100644 index 0000000000..9ef26331c1 --- /dev/null +++ b/board/freescale/imx8dxl_evk/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8DXL +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/configs/imx8dxl_evk_defconfig b/configs/imx8dxl_evk_defconfig new file mode 100644 index 0000000000..0a1cd29420 --- /dev/null +++ b/configs/imx8dxl_evk_defconfig @@ -0,0 +1,158 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 diff --git a/include/configs/imx8dxl_evk.h b/include/configs/imx8dxl_evk.h new file mode 100644 index 0000000000..acb0a3063f --- /dev/null +++ b/include/configs/imx8dxl_evk.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8DXL_EVK_H +#define __IMX8DXL_EVK_H + +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * So 3rd container image may start from 0x8181000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08181000 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +/* + * The memory layout on stack: DATA section save + gd + early malloc + * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with + * CONFIG_SYS_SPL_MALLOC_START + */ +#define CONFIG_SPL_STACK 0x822ffff0 +#define CONFIG_SPL_BSS_START_ADDR 0x82280000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x82200000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 + +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file imx8dxl-evk-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file imx8dxl-evk-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8dxl-evk-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* USDHC2 for SD */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 + +/* total DDR is 1GB */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define CONFIG_FEC_MXC_PHYADDR 0x1 + +#define DWC_NET_PHYADDR 0 + +#define CONFIG_ETHPRIME "eth1" + +#endif /* __IMX8DXL_EVK_H */ -- 2.17.1