From cb240778e689774ff03242d4c80d8f8fcde753b3 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Thu, 8 Jun 2017 10:16:25 +0800 Subject: [PATCH] MLK-15001-41 arm64: dtsi: fsl-imx8qxp-ldb: Add LDB support This patch adds LDB support. Signed-off-by: Liu Ying --- .../arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index 220c5cebe2e2..f5e133b39958 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -31,6 +31,8 @@ dpu0 = &dpu1; ethernet0 = &fec1; ethernet1 = &fec2; + ldb0 = &ldb1; + ldb1 = &ldb2; serial0 = &lpuart0; serial3 = &lpuart3; mmc0 = &usdhc1; @@ -771,9 +773,11 @@ reg = <0>; dpu_disp0_lvds0_ch0: lvds0-endpoint { + remote-endpoint = <&ldb1_ch0>; }; dpu_disp0_lvds0_ch1: lvds1-endpoint { + remote-endpoint = <&ldb1_ch1>; }; dpu_disp0_mipi_dsi: mipi-dsi-endpoint { @@ -784,9 +788,11 @@ reg = <1>; dpu_disp1_lvds1_ch0: lvds0-endpoint { + remote-endpoint = <&ldb2_ch0>; }; dpu_disp1_lvds1_ch1: lvds1-endpoint { + remote-endpoint = <&ldb2_ch1>; }; dpu_disp1_mipi_dsi: mipi-dsi-endpoint { @@ -806,6 +812,11 @@ power-domains = <&pd_mipi_dsi0>; }; + lvds_region1: lvds_region@56220000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56220000 0x0 0x10000>; + }; + ldb1_phy: ldb_phy@56221000 { compatible = "mixel,lvds-combo-phy"; reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; @@ -816,6 +827,52 @@ status = "disabled"; }; + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_mipi_dsi0>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch1>; + }; + }; + }; + }; + i2c0_mipi_lvds0: i2c@56226000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; reg = <0x0 0x56226000 0x0 0x1000>; @@ -842,6 +899,11 @@ power-domains = <&pd_mipi_dsi1>; }; + lvds_region2: lvds_region@56240000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + ldb2_phy: ldb_phy@56241000 { compatible = "mixel,lvds-combo-phy"; reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; @@ -852,6 +914,52 @@ status = "disabled"; }; + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_mipi_dsi1>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch1>; + }; + }; + }; + }; + i2c0_mipi_lvds1: i2c@56246000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; reg = <0x0 0x56246000 0x0 0x1000>; -- 2.17.1