From cac92301797f9a8d00d936994468769680b2351d Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Fri, 11 Sep 2020 15:30:34 +0800 Subject: [PATCH] MLK-24766-6 arm64: dts: imx8qxp-val: enable lpspi0 support Enable imx8qxp-lpddr4-val lpspi0 with cs-gpios and flash enabled. Signed-off-by: Clark Wang Reviewed-by: Ye Li (cherry picked from commit 45a2bee23109ade147e4582a9df11b8bc26fa46b) (cherry picked from commit 3bc8a257ae9bb5572feff0eecf04acb2df6eeeab) --- arch/arm/dts/fsl-imx8dx.dtsi | 33 ++++++++++++++++++++-- arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts | 37 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 3f361f9b94..4fa638f6ac 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -69,6 +69,7 @@ usbphy0 = &usbphy1; usb1 = &usbotg3; pci0 = &pcieb; + spi1 = &lpspi0; }; cpus { @@ -2750,11 +2751,25 @@ <&clk IMX8QXP_SPI0_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <80000000>; power-domains = <&pd_dma_lpspi0>; status = "disabled"; }; + lpspi1: lpspi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a010000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI1_CLK>, + <&clk IMX8QXP_SPI1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi1>; + status = "disabled"; + }; + lpspi2: lpspi@5a020000 { compatible = "fsl,imx7ulp-spi"; reg = <0x0 0x5a020000 0x0 0x10000>; @@ -2764,11 +2779,25 @@ <&clk IMX8QXP_SPI2_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <80000000>; power-domains = <&pd_dma_lpspi2>; status = "disabled"; }; + lpspi3: lpspi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a030000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI3_CLK>, + <&clk IMX8QXP_SPI3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi3>; + status = "disabled"; + }; + lpuart0: serial@5a060000 { compatible = "fsl,imx8qm-lpuart"; reg = <0x0 0x5a060000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts index c33ace9ad9..77e27a0205 100644 --- a/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts @@ -121,6 +121,20 @@ >; }; + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_ADMA_SPI0_SCK 0x600004c + SC_P_SPI0_SDO_ADMA_SPI0_SDO 0x600004c + SC_P_SPI0_SDI_ADMA_SPI0_SDI 0x600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 @@ -257,6 +271,10 @@ status = "okay"; }; +&gpio1 { + status = "okay"; +}; + &gpio3 { status = "okay"; }; @@ -265,6 +283,25 @@ status = "okay"; }; +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>, <0>, <0>, <0>; + spi-max-frequency = <1000000>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; -- 2.17.1