From c0e0789a12f0e07d5a8a2a89ad63e132adde6cfc Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 18 Apr 2018 03:34:31 -0700 Subject: [PATCH] MLK-16034-03: support NAND on i.MX8QXP ARM2 board NAND module is pin conflict with SD/eMMC on i.MX8QXP ARM2 board, add new config to disable SD/eMMC when booting from NAND. Signed-off-by: Han Xu Signed-off-by: Ye Li (cherry picked from commit 0a498b1f591fb00a0187650446e0de81dd3453ad) --- arch/arm/dts/Makefile | 1 + .../dts/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts | 52 +++++++++ board/freescale/imx8qxp_arm2/imx8qxp_arm2.c | 39 +------ configs/imx8qxp_lpddr4_arm2_nand_defconfig | 105 ++++++++++++++++++ include/configs/imx8qxp_arm2.h | 10 +- 5 files changed, 167 insertions(+), 40 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts create mode 100644 configs/imx8qxp_lpddr4_arm2_nand_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7192a544a0..2b273e544d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -553,6 +553,7 @@ dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb \ fsl-imx8qm-ddr4-arm2.dtb \ fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qxp-lpddr4-arm2.dtb \ + fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dtb \ fsl-imx8qxp-17x17-val.dtb \ fsl-imx8dx-17x17-val.dtb diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts new file mode 100644 index 0000000000..f6e5e4edb4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&iomuxc { + imx8qxp-arm2 { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + SC_P_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + SC_P_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + SC_P_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + SC_P_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c index 60ed635981..0dca6aedf6 100644 --- a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c +++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c @@ -60,6 +60,7 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_NAND_MXS static iomux_cfg_t gpmi_nand_pads[] = { SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), @@ -92,41 +93,16 @@ static void setup_iomux_gpmi_nand(void) static void imx8qxp_gpmi_nand_initialize(void) { int ret; -#ifdef CONFIG_SPL_BUILD - sc_ipc_t ipcHndl = 0; - - ipcHndl = gd->arch.ipc_channel_handle; - - ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_DMA_4_CH0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) - return; - - - ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_NAND, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) - return; -#else - struct power_domain pd; - - if (!power_domain_lookup_name("conn_dma4_ch0", &pd)) { - ret = power_domain_on(&pd); - if (ret) - printf("conn_dma4_ch0 Power up failed! (error = %d)\n", ret); - } - if (!power_domain_lookup_name("conn_nand", &pd)) { - ret = power_domain_on(&pd); - if (ret) - printf("conn_nand Power up failed! (error = %d)\n", ret); - } -#endif + ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return; init_clk_gpmi_nand(); setup_iomux_gpmi_nand(); - mxs_dma_init(); - } #endif +#endif static iomux_cfg_t uart0_pads[] = { SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -429,7 +405,6 @@ int board_phy_config(struct phy_device *phydev) } #endif - #define DEBUG_LED IMX_GPIO_NR(3, 23) #define IOEXP_RESET IMX_GPIO_NR(0, 19) #define BB_PWR_EN IMX_GPIO_NR(5, 9) @@ -596,10 +571,6 @@ int board_init(void) { board_gpio_init(); -#ifdef CONFIG_NAND_MXS - imx8qxp_gpmi_nand_initialize(); -#endif - return 0; } diff --git a/configs/imx8qxp_lpddr4_arm2_nand_defconfig b/configs/imx8qxp_lpddr4_arm2_nand_defconfig new file mode 100644 index 0000000000..d0bd1f92ec --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_nand_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_arm2/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_NAND=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2-gpmi-nand" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dtb" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_VIDEO=y + +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +# CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_NAND_BOOT=y +CONFIG_CMD_UBI=y + +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y diff --git a/include/configs/imx8qxp_arm2.h b/include/configs/imx8qxp_arm2.h index dbf1c39d0f..c2adc732a0 100644 --- a/include/configs/imx8qxp_arm2.h +++ b/include/configs/imx8qxp_arm2.h @@ -283,8 +283,7 @@ #define CONFIG_SERIAL_TAG -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS +#ifdef CONFIG_NAND_MXS #define CONFIG_CMD_NAND_TRIMFFS /* NAND stuff */ @@ -293,10 +292,9 @@ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION -/* DMA stuff, needed for GPMI/MXS NAND support */ -#define CONFIG_APBH_DMA -#define CONFIG_APBH_DMA_BURST -#define CONFIG_APBH_DMA_BURST8 +#ifdef CONFIG_CMD_UBI +#define CONFIG_MTD_DEVICE +#endif #endif /* USB Config */ -- 2.17.1