From bd9425135b3198164b0c1343a92e3f819f13451e Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Mon, 27 Apr 2020 00:20:14 +0200 Subject: [PATCH] arm: imx: Add eth0 net support to imx6ull_somdevices board. Signed-off-by: Josep Orga --- arch/arm/dts/imx6ull-somdevices.dts | 101 +++--------------- .../imx6ull_somdevices/imx6ull_somdevices.c | 9 ++ configs/imx6ull_somdevices_defconfig | 3 +- include/configs/imx6ull_somdevices.h | 6 +- net/eth-uclass.c | 11 ++ 5 files changed, 38 insertions(+), 92 deletions(-) diff --git a/arch/arm/dts/imx6ull-somdevices.dts b/arch/arm/dts/imx6ull-somdevices.dts index d0a2901134..c5d71f00a3 100644 --- a/arch/arm/dts/imx6ull-somdevices.dts +++ b/arch/arm/dts/imx6ull-somdevices.dts @@ -14,10 +14,6 @@ model = "Freescale i.MX6 ULL µSMARC SOMDEVICES Board"; compatible = "fsl,imx6ull-somdevices", "fsl,imx6ull"; - aliases { - spi5 = &soft_spi; - }; - chosen { stdout-path = &uart1; }; @@ -57,15 +53,6 @@ #address-cells = <1>; #size-cells = <0>; - reg_can_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; - }; - reg_sd1_vmmc: regulator@1 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -125,30 +112,6 @@ "ASRC-Capture", "CPU-Capture", "CPU-Capture", "Capture"; }; - - soft_spi: soft-spi { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - status = "okay"; - gpio-sck = <&gpio5 11 0>; - gpio-mosi = <&gpio5 10 0>; - cs-gpios = <&gpio5 7 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - registers-default = /bits/ 8 <0x57>; - spi-max-frequency = <100000>; - }; - }; }; &cpu0 { @@ -162,62 +125,37 @@ &csi { status = "okay"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - }; - }; }; &fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; phy-mode = "rmii"; phy-handle = <ðphy0>; status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - mdio { #address-cells = <1>; #size-cells = <0>; - ethphy0: ethernet-phy@2 { + ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - micrel,led-mode = <1>; + smsc,disable-energy-detect; + reg = <0>; clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_3v3>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_3v3>; status = "okay"; }; @@ -269,26 +207,6 @@ clock-names = "mclk"; wlf,shared-lrclk; }; - - ov5640: ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi1>; - clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "csi_mclk"; - pwn-gpios = <&gpio_spi 6 1>; - rst-gpios = <&gpio_spi 5 0>; - csi_id = <0>; - mclk = <24000000>; - mclk_source = <0>; - status = "okay"; - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi1_ep>; - }; - }; - }; }; &iomuxc { @@ -348,6 +266,13 @@ >; }; + pinctrl_enet1_mdio: mdioenet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + pinctrl_flexcan1: flexcan1grp{ fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 @@ -599,6 +524,8 @@ pinctrl_hog_2: hoggrp-2 { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0b0 //FEC1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x1b0b0 //FEC2 >; }; @@ -617,8 +544,6 @@ pinctrl_spi4: spi4grp { fsl,pins = < - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 >; diff --git a/board/somdevices/imx6ull_somdevices/imx6ull_somdevices.c b/board/somdevices/imx6ull_somdevices/imx6ull_somdevices.c index 961c789cc0..86c8637938 100644 --- a/board/somdevices/imx6ull_somdevices/imx6ull_somdevices.c +++ b/board/somdevices/imx6ull_somdevices/imx6ull_somdevices.c @@ -210,6 +210,15 @@ static int setup_fec(int fec_id) struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; + // PHY reset 1 + gpio_request(IMX_GPIO_NR(5, 10), "phy reset 1"); + gpio_direction_output(IMX_GPIO_NR(5, 10) , 1); + udelay(10000); + // PHY reset 2 + gpio_request(IMX_GPIO_NR(5, 11), "phy reset 2"); + gpio_direction_output(IMX_GPIO_NR(5, 11) , 1); + udelay(10000); + if (fec_id == 0) { if (check_module_fused(MX6_MODULE_ENET1)) return -1; diff --git a/configs/imx6ull_somdevices_defconfig b/configs/imx6ull_somdevices_defconfig index d09a39563e..108fca835e 100644 --- a/configs/imx6ull_somdevices_defconfig +++ b/configs/imx6ull_somdevices_defconfig @@ -42,7 +42,8 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y +# CONFIG_PHY_MICREL is not set +CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/include/configs/imx6ull_somdevices.h b/include/configs/imx6ull_somdevices.h index 73ae0e0863..55b40c629f 100644 --- a/include/configs/imx6ull_somdevices.h +++ b/include/configs/imx6ull_somdevices.h @@ -297,11 +297,11 @@ #ifdef CONFIG_FEC_MXC #define CONFIG_CMD_MII -#define CONFIG_FEC_ENET_DEV 1 +#define CONFIG_FEC_ENET_DEV 0 #if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_MXC_PHYADDR 0x0 #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "eth0" #elif (CONFIG_FEC_ENET_DEV == 1) @@ -311,7 +311,7 @@ #define CONFIG_ETHPRIME "eth1" #endif -#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_MDIO_BASE ENET_BASE_ADDR #endif #define CONFIG_IMX_THERMAL diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 4cef242ab8..518acef7b6 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -14,6 +14,7 @@ #include #include #include "eth_internal.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -442,6 +443,16 @@ int eth_initialize(void) putc('\n'); } + // PHY reset 1 + gpio_request(IMX_GPIO_NR(5, 10), "phy reset 1"); + gpio_direction_output(IMX_GPIO_NR(5, 10) , 0); + mdelay(25); + gpio_direction_output(IMX_GPIO_NR(5, 10) , 1); + // PHY reset 2 + gpio_request(IMX_GPIO_NR(5, 11), "phy reset 2"); + gpio_direction_output(IMX_GPIO_NR(5, 11) , 0); + mdelay(25); + gpio_direction_output(IMX_GPIO_NR(5, 11) , 1); return num_devices; } -- 2.17.1