From bd1f0385d1a408a5413d47db07ad78681f1caee0 Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Wed, 23 Aug 2017 15:39:33 +0800 Subject: [PATCH] MLK-16255-2 video: fbdev: dcss: use 'db' of ctxld to config DTG DTG is a standard double buffer module which has shadow registers. So use double buffer to config its registers via Context Loader. Signed-off-by: Fancy Fang --- drivers/video/fbdev/mxc/imx_dcss.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/video/fbdev/mxc/imx_dcss.c b/drivers/video/fbdev/mxc/imx_dcss.c index d4ce92eb5658..f493b7341462 100644 --- a/drivers/video/fbdev/mxc/imx_dcss.c +++ b/drivers/video/fbdev/mxc/imx_dcss.c @@ -1873,17 +1873,17 @@ static void dtg_channel_timing_config(int blank, switch (blank) { case FB_BLANK_UNBLANK: /* set display window for one channel */ - fill_sb(cb, chans->dtg_addr + ch_ulc_reg, + fill_db(cb, chans->dtg_addr + ch_ulc_reg, pos->ulc_y << 16 | pos->ulc_x); - fill_sb(cb, chans->dtg_addr + ch_lrc_reg, + fill_db(cb, chans->dtg_addr + ch_lrc_reg, pos->lrc_y << 16 | pos->lrc_x); break; case FB_BLANK_NORMAL: case FB_BLANK_VSYNC_SUSPEND: case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_POWERDOWN: - fill_sb(cb, chans->dtg_addr + ch_ulc_reg, 0x0); - fill_sb(cb, chans->dtg_addr + ch_lrc_reg, 0x0); + fill_db(cb, chans->dtg_addr + ch_ulc_reg, 0x0); + fill_db(cb, chans->dtg_addr + ch_lrc_reg, 0x0); break; default: return; @@ -1909,19 +1909,19 @@ static void dtg_global_timing_config(struct dcss_info *info) dmode->right_margin + dmode->hsync_len - 1; dtg_lrc_y = dmode->yres + dmode->upper_margin + dmode->lower_margin + dmode->vsync_len - 1; - fill_sb(cb, chans->dtg_addr + 0x4, dtg_lrc_y << 16 | dtg_lrc_x); + fill_db(cb, chans->dtg_addr + 0x4, dtg_lrc_y << 16 | dtg_lrc_x); /* Active Region Timing config*/ dis_ulc_x = dmode->left_margin + dmode->hsync_len - 1; dis_ulc_y = dmode->upper_margin + dmode->lower_margin + dmode->vsync_len - 1; - fill_sb(cb, chans->dtg_addr + 0x8, dis_ulc_y << 16 | dis_ulc_x); + fill_db(cb, chans->dtg_addr + 0x8, dis_ulc_y << 16 | dis_ulc_x); dis_lrc_x = dmode->xres + dmode->left_margin + dmode->hsync_len - 1; dis_lrc_y = dmode->yres + dmode->upper_margin + dmode->lower_margin + dmode->vsync_len - 1; - fill_sb(cb, chans->dtg_addr + 0xc, dis_lrc_y << 16 | dis_lrc_x); + fill_db(cb, chans->dtg_addr + 0xc, dis_lrc_y << 16 | dis_lrc_x); } static int dcss_dtg_config(uint32_t ch_id, struct dcss_info *info) @@ -2475,7 +2475,7 @@ static int dcss_channel_blank(int blank, return -EINVAL; } - fill_sb(cb, chans->dtg_addr + 0x0, dtg_ctrl); + fill_db(cb, chans->dtg_addr + 0x0, dtg_ctrl); return 0; } -- 2.17.1