From b8988c2dd7e1e5b235181e30db352453da582e48 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 23 May 2017 19:46:06 +0800 Subject: [PATCH] MLK-14968-2 ARM64: dts: fsl-imx8: add usdhc1 support HS400 mode Add usdhc1 support for HS200/HS400 mode for imx8qm and imx8qxp. Signed-off-by: Haibo Chen --- .../dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 43 +++++++++++++++++-- arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 5 ++- .../dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts | 43 +++++++++++++++++-- .../arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 5 ++- 4 files changed, 88 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 8d5f77f5d51f..afc532031e58 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -130,7 +130,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 @@ -140,13 +140,48 @@ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 @@ -229,8 +264,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 97e746abce79..3b7b3817732a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -1379,8 +1379,11 @@ <&clk IMX8QM_SDHC0_CLK>, <&clk IMX8QM_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; - assigned-clock-rates = <400000000>, <200000000>, <0>; + assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; + assigned-clock-rates = <400000000>; power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts index 3c908bbadf18..08a467baf3d4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts @@ -107,7 +107,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 @@ -117,6 +117,41 @@ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 >; }; @@ -129,7 +164,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021 @@ -199,8 +234,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index 6b8230740c70..069b5abbccfc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -922,8 +922,11 @@ <&clk IMX8QXP_SDHC0_CLK>, <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; - assigned-clock-rates = <400000000>, <200000000>, <0>; + assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-rates = <400000000>; power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; -- 2.17.1