From b895e1a143ad88ece23cc633fb00b4974363d0a0 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 1 Jun 2018 00:22:46 -0700 Subject: [PATCH] MLK-18476-2 mx6qdl_arm2: Add MX6Q and DL ARM2 support Porting the iMX6Q DDR3/LPDDR2 ARM2, iMX6DL DDR3/LPDDR2 ARM2 and iMX6Q POP LPDDR2 ARM2 board codes from v2019.04. Signed-off-by: Ye Li (cherry picked from commit 8ce8ab2f9b875fe43489d7624a296f036e43e585) (cherry picked from commit 34d29f3cdbf5e9f30ff9593295af4c85d3833ee3) (cherry picked from commit 6f8ff60c04d8c5ab1e017db45ef6909f2d31447f) (cherry picked from commit db4431dcb4e8e4fd7a484564b3e0c806f6faa9be) --- arch/arm/mach-imx/mx6/Kconfig | 15 + board/freescale/mx6qarm2/Kconfig | 8 +- board/freescale/mx6qarm2/imximage.cfg | 188 ++- board/freescale/mx6qarm2/imximage_mx6dl.cfg | 15 +- board/freescale/mx6qarm2/mt128x64mx32.cfg | 301 +++++ board/freescale/mx6qarm2/mx6qarm2.c | 121 +- board/freescale/mx6qarm2/plugin.S | 1176 +++++++++++++++++++ include/configs/mx6qarm2.h | 17 +- 8 files changed, 1792 insertions(+), 49 deletions(-) create mode 100644 board/freescale/mx6qarm2/mt128x64mx32.cfg create mode 100644 board/freescale/mx6qarm2/plugin.S diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index a45958a6bc..9b444e810b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -144,6 +144,14 @@ config TARGET_MX6SABRESD_COMMON select NXP_BOARD_REVISION imply CMD_DM +config TARGET_MX6QDLARM2 + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + imply CMD_DM + choice prompt "MX6 board select" optional @@ -341,6 +349,13 @@ config TARGET_MX6MEMCAL config TARGET_MX6QARM2 bool "mx6qarm2" + depends on MX6Q + select TARGET_MX6QDLARM2 + +config TARGET_MX6DLARM2 + bool "mx6dlarm2" + depends on MX6DL + select TARGET_MX6QDLARM2 config TARGET_MX6DL_MAMOJ bool "Support BTicino Mamoj" diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig index 8ab8b460f9..6d2c75151c 100644 --- a/board/freescale/mx6qarm2/Kconfig +++ b/board/freescale/mx6qarm2/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6QARM2 +if TARGET_MX6QARM2 || TARGET_MX6DLARM2 config SYS_BOARD default "mx6qarm2" @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6qarm2" +config SYS_TEXT_BASE + default 0x17800000 + +config MX6DQ_POP_LPDDR2 + bool "Select this if it is a MX6Q POP LPDDR2 board" + endif diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index 74a33c2503..7d27529bfe 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. * Jason Liu * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure @@ -9,6 +9,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include + /* image version */ IMAGE_VERSION 2 @@ -18,6 +21,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + /* * Device Configuration Data (DCD) * @@ -29,8 +41,179 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ -#ifdef CONFIG_MX6DQ_LPDDR2 +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* DCD */ +DATA 4 0x020e0798 0x00080000 +DATA 4 0x020e0758 0x00000000 + +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 + +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 + +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 + +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00003030 +DATA 4 0x020e05b0 0x00003030 +DATA 4 0x020e0524 0x00003030 +DATA 4 0x020e051c 0x00003030 +DATA 4 0x020e0518 0x00003030 +DATA 4 0x020e050c 0x00003030 +DATA 4 0x020e05b8 0x00003030 +DATA 4 0x020e05c0 0x00003030 + +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 + +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1B5F0107 +DATA 4 0x021b485c 0x1B5F0107 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b0848 0x3C3A3A44 +DATA 4 0x021b4848 0x3C3A3A44 + +DATA 4 0x021b0850 0x4238423A +DATA 4 0x021b4850 0x4238423A + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x00000000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b000c 0x444961A5 +DATA 4 0x021b0010 0x00160E83 +DATA 4 0x021b0014 0x000000DD + +DATA 4 0x021b0018 0x0000174C +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x149F26D2 +DATA 4 0x021b0030 0x00000010 +DATA 4 0x021b0038 0x0021099B +DATA 4 0x021b0040 0x0000004F +DATA 4 0x021b0400 0x11420000 +DATA 4 0x021b0000 0x83110000 + +DATA 4 0x021b4004 0x00020036 +DATA 4 0x021b4008 0x00000000 +DATA 4 0x021b400c 0x444961A5 +DATA 4 0x021b4010 0x00160E83 +DATA 4 0x021b4014 0x000000DD + +DATA 4 0x021b4018 0x0000174C +DATA 4 0x021b401c 0x00008000 +DATA 4 0x021b402c 0x149F26D2 +DATA 4 0x021b4030 0x00000010 +DATA 4 0x021b4038 0x0021099B +DATA 4 0x021b4040 0x00000017 +DATA 4 0x021b4400 0x11420000 +DATA 4 0x021b4000 0x83110000 + +DATA 4 0x021b001c 0x003F8030 +DATA 4 0x021b001c 0xFF0A8030 +DATA 4 0x021b001c 0xC2018030 +DATA 4 0x021b001c 0x06028030 +DATA 4 0x021b001c 0x02038030 + +DATA 4 0x021b401c 0x003F8030 +DATA 4 0x021b401c 0xFF0A8030 +DATA 4 0x021b401c 0xC2018030 +DATA 4 0x021b401c 0x06028030 +DATA 4 0x021b401c 0x02038030 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b4020 0x00001800 + +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b4818 0x00000000 + +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b4004 0x00025576 + +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b4404 0x00011006 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b401c 0x00000000 + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +#elif defined(CONFIG_MX6DQ_LPDDR2) /* DCD */ +DATA 4 0x020C4018 0x21324 +DATA 4 0x020C4014 0x2018D00 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x61324 +DATA 4 0x020C4014 0x18D00 +CHECK_BITS_CLR 4 0x020C4048 0x3F DATA 4 0x020C4018 0x60324 DATA 4 0x020E05a8 0x00003038 @@ -335,3 +518,4 @@ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DQ_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index 0d1353119b..386d21f8e0 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * Jason Liu * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure @@ -9,6 +9,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include + /* image version */ IMAGE_VERSION 2 @@ -18,6 +21,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + /* * Device Configuration Data (DCD) * @@ -459,3 +471,4 @@ DATA 4 0x020e0010 0xF00000CF DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DL_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg new file mode 100644 index 0000000000..8fe02fcb88 --- /dev/null +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_MX6DQ_POP_LPDDR2 +/* set ddr to 400Mhz */ +DATA 4 0x020C4018 0x21324 +DATA 4 0x020C4014 0x2018100 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x61324 +DATA 4 0x020C4014 0x18900 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x60324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff +// Switch PL301_FAST2 to DDR dual channel mapping +//DATA 4 0x00B00000 0x1 + +//============================================================================= +/// IOMUX +//============================================================================= +//DDR IO TYPE: +DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE +DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE + +//CLOCK: +DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 +DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + +//Control: +DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS +DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS +DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET +DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS +DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 +DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 +DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS +DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS + +//Data Strobes: +DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL +DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 +DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 +DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 +DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 +DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 +DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 +DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 +DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 + +//Data: +DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE +DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS +DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS +DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS +DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS +DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS +DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS +DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS +DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS + +DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 +DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 +DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 +DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 +DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 +DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 +DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 +DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 + +//============================================================================= +// DDR Controller Registers +//============================================================================= +// Manufacturer: Micron - POP Package +// Device Part Number: MT42L128M64D2LL-25WT +// Clock Freq.: 400MHz +// Density per CS in Gb: 4 +// Chip Selects used: 1 +// Number of channels 2 +// Density per channel (Gb) 4 +// Total DRAM density (Gb) 8 +// Number of Banks: 8 +// Row address: 14 +// Column address: 10 +// Data bus width 32 +//============================================================================= + +// MMDC0_MDSCR, set the Configuration request bit during MMDC set up +DATA 4 0x021b001c 0x00008000 // Chan 0 +DATA 4 0x021b401c 0x00008000 // Chan 1 +// Adjust ZQ delay for MMDC clock frequency at 400MHz +DATA 4 0x021b085c 0x1b4700c7 //LPDDR2 ZQ params +DATA 4 0x021b485c 0x1b4700c7 //LPDDR2 ZQ params + +//============================================================================= +// Calibration setup. +// +//============================================================================= +DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration +DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL + +DATA 4 0x021b0890 0x00400000 //ca bus abs delay +DATA 4 0x021b4890 0x00400000 //ca bus abs delay + +//DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL + +DATA 4 0x021b08b8 0x00000800 //frc_msr. +DATA 4 0x021b48b8 0x00000800 //frc_msr. + +// read delays, settings recommended by design to remain constant +DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 +DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 +DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 +DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 +DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3 +DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3 +DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3 +DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 + +// write delays, settings recommended by design to remain constant +DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 + +DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0 +DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1 + +DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0 +DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1 + +DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis +DATA 4 0x021b4840 0x0 + +//For i.mx6qd parts of versions C and later (v1.2, v1.3). +DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 +DATA 4 0x021b48c0 0x24921492 + +DATA 4 0x021b08b8 0x00000800 //frc_msr. +DATA 4 0x021b48b8 0x00000800 //frc_msr. +//============================================================================= +// Calibration setup end +//============================================================================= + +// Channel0 - starting address 0x80000000 +DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0 +DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC +DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1 +DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2 + +//MDMISC: RALAT kept to the high level of 5. +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: +//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 +//b. Small performence improvment +DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC +DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD +DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR +DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP +DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC +DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode +// DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled +DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL + +// Channel1 - starting address 0x10000000 +// Note: the values for Chan1 should match those of Chan0 +DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0 +DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC +DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1 +DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2 +DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC +DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD +DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR +DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP +DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC +DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END +// DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled +DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL + +// Precharge all commands per JEDEC +// The memory controller may optionally issue a Precharge-All command +// prior to the MRW Reset command. +// This is strongly recommended to ensure a robust DRAM initialization +DATA 4 0x021b001c 0x00008010 // precharge-all commnad CS0 - Chan 0 +DATA 4 0x021b401c 0x00008010 // precharge-all commnad CS0 - Chan 1 + +//============================================================================= +// LPDDR2 Mode Register Writes +//============================================================================= +// Channel 0 CS0 +DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) +DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration +DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration +DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration +// Channel 0 CS1 +// Note, CS1 does not exist in this memory hence these writes are commented out +// They are only shown here for completeness +// If you use a memory where CS1 exists, simply uncomment these lines +//DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) +//DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +//DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration +//DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration +//DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration + +// For Channel 1 mode register writes - these should match channel 0 settings +// Channel 1 CS0 +DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) +DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration +DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration +DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration +// Channel 1 CS1 +// Note, CS1 does not exist in this memory hence these writes are commented out +// They are only shown here for completeness +// If you use a memory where CS1 exists, simply uncomment these lines +//DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) +//DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +//DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration +//DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration +//DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration + +//////////#################################################// +//final DDR setup, before operation start: + +DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF +DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting + +DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL +DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL + +DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr +DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr + +DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled +DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting + +DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled +DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting + +DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register +DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif +#endif diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index c06fd64367..0c3d100419 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -14,11 +14,13 @@ #include #include #include +#include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -33,6 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ @@ -45,11 +51,24 @@ int dram_init(void) return 0; } +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} +#endif + iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_DM_MMC iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -61,7 +80,11 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#else MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +#endif }; iomux_v3_cfg_t const usdhc4_pads[] = { @@ -76,6 +99,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#endif iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -107,27 +131,24 @@ static void setup_iomux_enet(void) } #ifdef CONFIG_FSL_ESDHC_IMX +#ifndef CONFIG_DM_MMC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; -int board_mmc_get_env_dev(int devno) -{ - return devno - 2; -} - int board_mmc_getcd(struct mmc *mmc) { + int ret = 1; +#ifndef CONFIG_MX6DQ_POP_LPDDR2 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(6, 11)); ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); } else /* Don't have the CD GPIO pin on board */ ret = 1; - +#endif return ret; } @@ -164,70 +185,61 @@ int board_mmc_init(struct bd_info *bis) return 0; } #endif +#endif #define MII_MMD_ACCESS_CTRL_REG 0xd #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe #define MII_DBG_PORT_REG 0x1d #define MII_DBG_PORT2_REG 0x1e -int fecmxc_mii_postcall(int phy) +static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; - /* - * Due to the i.MX6Q Armadillo2 board HW design,there is - * no 125Mhz clock input from SOC. In order to use RGMII, - * We need enable AR8031 ouput a 125MHz clk from CLK_25M - */ - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); - miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_CTRL_REG, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_CTRL_REG, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG); val &= 0xffe3; val |= 0x18; - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG, val); - /* For the RGMII phy, we need enable tx clock delay */ - miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); - miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT_REG, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT2_REG); val |= 0x0100; - miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); - - miiphy_write("FEC", phy, MII_BMCR, 0xa100); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT2_REG, val); return 0; } -int board_eth_init(struct bd_info *bis) +int board_phy_config(struct phy_device *phydev) { - struct eth_device *dev; - int ret = cpu_eth_init(bis); + ar8031_phy_fixup(phydev); - if (ret) - return ret; + if (phydev->drv->config) + phydev->drv->config(phydev); - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } + return 0; +} - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } +int board_eth_init(struct bd_info *bis) +{ + setup_iomux_enet(); - return 0; + return cpu_eth_init(bis); } #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; static void setup_usb(void) @@ -257,11 +269,11 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif int board_early_init_f(void) { setup_iomux_uart(); - setup_iomux_enet(); return 0; } @@ -272,7 +284,24 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); +#else + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 1); +#endif +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); #endif return 0; @@ -288,3 +317,11 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_LDO_BYPASS_CHECK +/* no external pmic, always ldo_enable */ +void ldo_mode_set(int ldo_bypass) +{ + return; +} +#endif diff --git a/board/freescale/mx6qarm2/plugin.S b/board/freescale/mx6qarm2/plugin.S new file mode 100644 index 0000000000..fe697598e3 --- /dev/null +++ b/board/freescale/mx6qarm2/plugin.S @@ -0,0 +1,1176 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.macro imx6dlarm2_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00003000 + str r1, [r0, #0x590] + str r1, [r0, #0x598] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00003030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x00370037 + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x422f0220 + str r2, [r0, #0x83c] + ldr r2, =0x021f0219 + str r2, [r0, #0x840] + + ldr r2, =0x422f0220 + str r2, [r1, #0x83c] + ldr r2, =0x022d022f + str r2, [r1, #0x840] + + ldr r2, =0x47494b49 + str r2, [r0, #0x848] + ldr r2, =0x48484c47 + str r2, [r1, #0x848] + + ldr r2, =0x39382b2f + str r2, [r0, #0x850] + ldr r2, =0x2f35312c + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x00000800 + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x40445323 + str r2, [r0, #0x00c] + ldr r2, =0xb66e8c63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00081740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00440e21 + str r2, [r0, #0x030] + +#ifdef CONFIG_DDR_32BIT + ldr r2, =0x00000017 + str r2, [r0, #0x040] + ldr r2, =0xc3190000 + str r2, [r0, #0x000] +#else + ldr r2, =0x00000027 + str r2, [r0, #0x040] + ldr r2, =0xc31a0000 + str r2, [r0, #0x000] +#endif + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x0400803a + str r2, [r0, #0x01c] + + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x0000803b + str r2, [r0, #0x01c] + + ldr r2, =0x00428031 + str r2, [r0, #0x01c] + ldr r2, =0x00428039 + str r2, [r0, #0x01c] + + ldr r2, =0x07208030 + str r2, [r0, #0x01c] + ldr r2, =0x07208038 + str r2, [r0, #0x01c] + + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x04008048 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + + ldr r2, =0x00000007 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r1, #0x004] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqarm2_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + ldr r1, =0x00000030 + str r1, [r0, #0x594] + + ldr r1, =0x00000030 + str r1, [r0, #0x56c] + ldr r1, =0x00000030 + str r1, [r0, #0x578] + ldr r1, =0x00000030 + str r1, [r0, #0x74c] + + ldr r1, =0x00000030 + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + ldr r1, =0x00000030 + str r1, [r0, #0x5a0] + ldr r1, =0x00000030 + str r1, [r0, #0x78c] + + ldr r1, =0x00000000 + str r1, [r0, #0x750] + + ldr r1, =0x00000038 + str r1, [r0, #0x5a8] + ldr r1, =0x00000038 + str r1, [r0, #0x5b0] + ldr r1, =0x00000038 + str r1, [r0, #0x524] + ldr r1, =0x00000038 + str r1, [r0, #0x51c] + ldr r1, =0x00000038 + str r1, [r0, #0x518] + ldr r1, =0x00000038 + str r1, [r0, #0x50c] + ldr r1, =0x00000038 + str r1, [r0, #0x5b8] + ldr r1, =0x00000038 + str r1, [r0, #0x5c0] + + ldr r1, =0x00000000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + ldr r1, =0x00000030 + str r1, [r0, #0x788] + ldr r1, =0x00000030 + str r1, [r0, #0x794] + ldr r1, =0x00000030 + str r1, [r0, #0x79c] + ldr r1, =0x00000030 + str r1, [r0, #0x7a0] + ldr r1, =0x00000030 + str r1, [r0, #0x7a4] + ldr r1, =0x00000030 + str r1, [r0, #0x7a8] + ldr r1, =0x00000030 + str r1, [r0, #0x748] + + ldr r1, =0x00000030 + str r1, [r0, #0x5ac] + ldr r1, =0x00000030 + str r1, [r0, #0x5b4] + ldr r1, =0x00000030 + str r1, [r0, #0x528] + ldr r1, =0x00000030 + str r1, [r0, #0x520] + ldr r1, =0x00000030 + str r1, [r0, #0x514] + ldr r1, =0x00000030 + str r1, [r0, #0x510] + ldr r1, =0x00000030 + str r1, [r0, #0x5bc] + ldr r1, =0x00000030 + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + ldr r2, =0x001F001F + str r2, [r0, #0x810] + + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00440044 + str r2, [r1, #0x80c] + ldr r2, =0x00440044 + str r2, [r1, #0x810] + + ldr r2, =0x4333033F + str r2, [r0, #0x83c] + ldr r2, =0x0339033E + str r2, [r0, #0x840] + ldr r2, =0x433F0343 + str r2, [r1, #0x83c] + ldr r2, =0x03490320 + str r2, [r1, #0x840] + + ldr r2, =0x42363838 + str r2, [r0, #0x848] + ldr r2, =0x3F343242 + str r2, [r1, #0x848] + + ldr r2, =0x37424844 + str r2, [r0, #0x850] + ldr r2, =0x48264731 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + ldr r2, =0x33333333 + str r2, [r0, #0x820] + ldr r2, =0x33333333 + str r2, [r0, #0x824] + ldr r2, =0x33333333 + str r2, [r0, #0x828] + ldr r2, =0x33333333 + str r2, [r1, #0x81c] + ldr r2, =0x33333333 + str r2, [r1, #0x820] + ldr r2, =0x33333333 + str r2, [r1, #0x824] + ldr r2, =0x33333333 + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x00000800 + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00081740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005a1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x11420000 + str r2, [r0, #0x400] + ldr r2, =0x11420000 + str r2, [r1, #0x400] + + ldr r2, =0xc31a0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x0408803a + str r2, [r0, #0x01c] + + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x0000803b + str r2, [r0, #0x01c] + + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x00048039 + str r2, [r0, #0x01c] + + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x09408038 + str r2, [r0, #0x01c] + + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x04008048 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlarm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00003028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00000038 + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x494] + str r1, [r0, #0x4a4] + str r1, [r0, #0x4a8] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + ldr r1, =0x00000038 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x74c] + str r1, [r0, #0x76c] + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + ldr r1, =0x00020000 + str r1, [r0, #0x760] + ldr r1, =0x00080000 + str r1, [r0, #0x774] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1b5f01ff + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x00055555 + str r2, [r1, #0x8bc] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x4b4b524f + str r2, [r0, #0x848] + ldr r2, =0x494f4c44 + str r2, [r1, #0x848] + + ldr r2, =0x3c3d303c + str r2, [r0, #0x850] + ldr r2, =0x3c343d38 + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + str r2, [r1, #0x840] + + ldr r2, =0x00000a00 + str r2, [r0, #0x858] + str r2, [r1, #0x858] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x34386145 + str r2, [r0, #0xc] + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00100c83 + str r2, [r0, #0x10] + ldr r2, =0x000000Dc + str r2, [r0, #0x14] + ldr r2, =0x0000174C + str r2, [r0, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x2c] + ldr r2, =0x0000020e + str r2, [r0, #0x30] + ldr r2, =0x00190778 + str r2, [r0, #0x38] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + + ldr r2, =0x0000005f + str r2, [r0, #0x40] + ldr r2, =0x0000000f + str r2, [r0, #0x404] + + ldr r2, =0xc3010000 + str r2, [r0, #0x0] + + ldr r2, =0x34386145 + str r2, [r1, #0xc] + + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00100c83 + str r2, [r1, #0x10] + ldr r2, =0x000000Dc + str r2, [r1, #0x14] + ldr r2, =0x0000174C + str r2, [r1, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r1, #0x2c] + ldr r2, =0x0000020e + str r2, [r1, #0x30] + ldr r2, =0x00190778 + str r2, [r1, #0x38] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + + ldr r2, =0x0000003f + str r2, [r1, #0x40] + + ldr r2, =0xc3010000 + str r2, [r1, #0x0] + + ldr r2, =0x003f8030 + str r2, [r0, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x1c] + ldr r2, =0xa2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x01038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003f8030 + str r2, [r1, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r1, #0x1c] + ldr r2, =0xa2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x01038030 + str r2, [r1, #0x1c] + + ldr r2, =0x00005800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6dqarm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x60324 + str r1, [r0, #0x18] + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00003038 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00000038 + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x57c] + str r1, [r0, #0x590] + str r1, [r0, #0x598] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + ldr r1, =0x00000038 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x74c] + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + ldr r1, =0x00020000 + str r1, [r0, #0x774] + ldr r1, =0x00000038 + str r1, [r0, #0x78c] + ldr r1, =0x00080000 + str r1, [r0, #0x798] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1b5f01ff + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xa1390000 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x00055555 + str r2, [r1, #0x8bc] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0xf3333333 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + str r2, [r1, #0x82c] + str r2, [r1, #0x830] + str r2, [r1, #0x834] + str r2, [r1, #0x838] + + ldr r2, =0x49383b39 + str r2, [r0, #0x848] + ldr r2, =0x30364738 + str r2, [r0, #0x850] + + ldr r2, =0x3e3c3846 + str r2, [r1, #0x848] + ldr r2, =0x4c294b35 + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + str r2, [r1, #0x840] + + ldr r2, =0x00000f00 + str r2, [r0, #0x858] + str r2, [r1, #0x858] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x555a61a5 + str r2, [r0, #0xc] + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00160e83 + str r2, [r0, #0x10] + ldr r2, =0x000000dd + str r2, [r0, #0x14] + ldr r2, =0x0008174C + str r2, [r0, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x2c] + ldr r2, =0x0000020e + str r2, [r0, #0x30] + ldr r2, =0x200aac + str r2, [r0, #0x38] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + + ldr r2, =0x0000005f + str r2, [r0, #0x40] + + ldr r2, =0xc3010000 + str r2, [r0, #0x0] + + ldr r2, =0x555a61a5 + str r2, [r1, #0xc] + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00160e83 + str r2, [r1, #0x10] + ldr r2, =0x000000dd + str r2, [r1, #0x14] + ldr r2, =0x0008174C + str r2, [r1, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r1, #0x2c] + ldr r2, =0x0000020e + str r2, [r1, #0x30] + ldr r2, =0x00200aac + str r2, [r1, #0x38] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + + ldr r2, =0x0000003f + str r2, [r1, #0x40] + + ldr r2, =0xc3010000 + str r2, [r1, #0x0] + + ldr r2, =0x003f8030 + str r2, [r0, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x1c] + ldr r2, =0xc2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x02038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003f8030 + str r2, [r1, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r1, #0x1c] + ldr r2, =0xc2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x02038030 + str r2, [r1, #0x1c] + + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x00007800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6dq_pop_arm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + str r1, [r0, #0x58c] + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00003030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1B5F0107 + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xA1390003 + str r2, [r0, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x3C3A3A44 + str r2, [r0, #0x848] + str r2, [r1, #0x848] + ldr r2, =0x4238423A + str r2, [r0, #0x850] + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x20000000 + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r1, #0x840] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0xf3333333 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + str r2, [r1, #0x82c] + str r2, [r1, #0x830] + str r2, [r1, #0x834] + str r2, [r1, #0x838] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + ldr r2, =0x444961A5 + str r2, [r0, #0xc] + ldr r2, =0x00160E83 + str r2, [r0, #0x10] + ldr r2, =0x000000DD + str r2, [r0, #0x14] + + ldr r2, =0x0000174C + str r2, [r0, #0x18] + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x149F26D2 + str r2, [r0, #0x2c] + ldr r2, =0x00000010 + str r2, [r0, #0x30] + ldr r2, =0x0021099B + str r2, [r0, #0x38] + ldr r2, =0x0000004F + str r2, [r0, #0x40] + ldr r2, =0x11420000 + str r2, [r0, #0x400] + ldr r2, =0x83110000 + str r2, [r0, #0x0] + + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + ldr r2, =0x444961A5 + str r2, [r1, #0xc] + ldr r2, =0x00160E83 + str r2, [r1, #0x10] + ldr r2, =0x000000DD + str r2, [r1, #0x14] + + ldr r2, =0x0000174C + str r2, [r1, #0x18] + ldr r2, =0x00008000 + str r2, [r1, #0x1c] + ldr r2, =0x149F26D2 + str r2, [r1, #0x2c] + ldr r2, =0x00000010 + str r2, [r1, #0x30] + ldr r2, =0x0021099B + str r2, [r1, #0x38] + ldr r2, =0x00000017 + str r2, [r1, #0x40] + ldr r2, =0x11420000 + str r2, [r1, #0x400] + ldr r2, =0x83110000 + str r2, [r1, #0x0] + + ldr r2, =0x003F8030 + str r2, [r0, #0x1c] + ldr r2, =0xFF0A8030 + str r2, [r0, #0x1c] + ldr r2, =0xC2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x02038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003F8030 + str r2, [r1, #0x1c] + ldr r2, =0xFF0A8030 + str r2, [r1, #0x1c] + ldr r2, =0xC2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x02038030 + str r2, [r1, #0x1c] + + ldr r2, =0xA1390003 + str r2, [r0, #0x800] + + ldr r2, =0x00001800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x00025576 + str r2, [r0, #0x4] + str r2, [r1, #0x4] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + str r2, [r1, #0x404] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6_ddr_setting + #if defined (CONFIG_MX6DQ_POP_LPDDR2) + imx6dq_pop_arm2_lpddr2_setting + #elif defined (CONFIG_MX6DQ_LPDDR2) + imx6dqarm2_lpddr2_setting + #elif defined (CONFIG_MX6Q) + imx6dqarm2_ddr_setting + #elif defined (CONFIG_MX6DL_LPDDR2) + imx6dlarm2_lpddr2_setting + #elif defined (CONFIG_MX6DL) + imx6dlarm2_ddr_setting + #else + #error "SOC not configured" + #endif +.endm + +.macro imx6_clock_gating +.endm + +.macro imx6_qos_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 83c09ead27..239f368c9f 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -10,6 +10,8 @@ #include "mx6_common.h" +#define CONFIG_IMX_THERMAL + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -24,19 +26,23 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ @@ -103,6 +109,10 @@ /* Miscellaneous configurable options */ /* Physical Memory Map */ +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +#define PHYS_SDRAM_0 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_1 MMDC1_ARB_BASE_ADDR +#endif #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM @@ -115,6 +125,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* SDHC4 */ /* USB Configs */ #ifdef CONFIG_CMD_USB -- 2.17.1