From b4fb31a8450622b74135bc9247734689ea4eef41 Mon Sep 17 00:00:00 2001 From: Arulpandiyan Vadivel Date: Thu, 10 Jan 2019 15:11:50 +0530 Subject: [PATCH] ARM: dts: imx6qp.dtsi: update node naming standards for 4.19 Fix below compilation warnings by adhering to 4.19 node naming standards. Warning (reg_format): /soc/aips-bus@02100000/pre@021c8000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): /soc/aips-bus@02100000/pre@021c9000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): /soc/aips-bus@02100000/pre@021ca000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): /soc/aips-bus@02100000/pre@021cb000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): /soc/aips-bus@02100000/prg@021cc000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): /soc/aips-bus@02100000/prg@021cd000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Signed-off-by: Arulpandiyan Vadivel --- arch/arm/boot/dts/imx6qp.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 0a269a1bd1ed..f7f22735f384 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -53,8 +53,8 @@ status = "disabled"; }; - aips-bus@02100000 { /* AIPS2 */ - pre1: pre@021c8000 { + aips-bus@2100000 { /* AIPS2 */ + pre1: pre@21c8000 { compatible = "fsl,imx6q-pre"; reg = <0x021c8000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRE0>; @@ -63,7 +63,7 @@ status = "disabled"; }; - pre2: pre@021c9000 { + pre2: pre@21c9000 { compatible = "fsl,imx6q-pre"; reg = <0x021c9000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRE1>; @@ -72,7 +72,7 @@ status = "disabled"; }; - pre3: pre@021ca000 { + pre3: pre@21ca000 { compatible = "fsl,imx6q-pre"; reg = <0x021ca000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRE2>; @@ -81,7 +81,7 @@ status = "disabled"; }; - pre4: pre@021cb000 { + pre4: pre@21cb000 { compatible = "fsl,imx6q-pre"; reg = <0x021cb000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRE3>; @@ -90,7 +90,7 @@ status = "disabled"; }; - prg1: prg@021cc000 { + prg1: prg@21cc000 { compatible = "fsl,imx6q-prg"; reg = <0x021cc000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG0_AXI>, @@ -100,7 +100,7 @@ status = "disabled"; }; - prg2: prg@021cd000 { + prg2: prg@21cd000 { compatible = "fsl,imx6q-prg"; reg = <0x021cd000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG1_AXI>, -- 2.17.1