From b2a90adf3f4a798cc81e2715e334e93538748621 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 11 Dec 2015 21:37:20 +0800 Subject: [PATCH] MLK-11995-2 ARM: imx: add DDR pad low power mode for i.mx7d In low power idle of i.MX7D, DDR controller should put DDR pads into low power mode, TO1.1 adds this support, after implementing this feature, NVCC_DRAM power can be lower from ~6mA to ~2mA in low power idle mode. Signed-off-by: Anson Huang --- arch/arm/mach-imx/cpuidle-imx7d.c | 9 +++++++-- arch/arm/mach-imx/imx7d_low_power_idle.S | 22 ++++++++++++++++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/cpuidle-imx7d.c b/arch/arm/mach-imx/cpuidle-imx7d.c index f92b76b19b14..4ba99d87db2b 100644 --- a/arch/arm/mach-imx/cpuidle-imx7d.c +++ b/arch/arm/mach-imx/cpuidle-imx7d.c @@ -73,6 +73,7 @@ struct imx7_cpuidle_pm_info { struct imx7_pm_base ccm_base; struct imx7_pm_base anatop_base; struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; } __aligned(8); static atomic_t master_lpi = ATOMIC_INIT(0); @@ -145,8 +146,8 @@ static struct cpuidle_driver imx7d_cpuidle_driver = { }, /* LOW POWER IDLE */ { - .exit_latency = 100, - .target_residency = 200, + .exit_latency = 300, + .target_residency = 500, .flags = CPUIDLE_FLAG_TIMER_STOP, .enter = imx7d_enter_low_power_idle, .name = "LOW-POWER-IDLE", @@ -252,6 +253,10 @@ int __init imx7d_cpuidle_init(void) cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + cpuidle_pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + cpuidle_pm_info->iomuxc_gpr_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + imx7d_enable_rcosc(); /* code size should include cpuidle_pm_info size */ diff --git a/arch/arm/mach-imx/imx7d_low_power_idle.S b/arch/arm/mach-imx/imx7d_low_power_idle.S index 070b457c8fc1..5fb35f4911ca 100644 --- a/arch/arm/mach-imx/imx7d_low_power_idle.S +++ b/arch/arm/mach-imx/imx7d_low_power_idle.S @@ -33,6 +33,8 @@ #define PM_INFO_MX7D_ANATOP_V_OFFSET 0x40 #define PM_INFO_MX7D_SRC_P_OFFSET 0x44 #define PM_INFO_MX7D_SRC_V_OFFSET 0x48 +#define PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET 0x4c +#define PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET 0x50 #define MX7D_SRC_GPR1 0x74 #define MX7D_SRC_GPR2 0x78 @@ -248,11 +250,31 @@ orr r7, r7, #(1 << 3) str r7, [r10, #DDRC_PWRCTL] + ldr r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + ldr r7, =0xf0000 + str r7, [r10] + + ldr r7, =0x10000 +11: + subs r7, r7, #0x1 + bne 11b + .endm /* r10 must be DDRC base address */ .macro ddrc_exit_self_refresh + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + ldr r7, =0x0 + str r7, [r10] + + ldr r7, =0x10000 +12: + subs r7, r7, #0x1 + bne 12b + cmp r5, #0x1 ldreq r10, [r0, #PM_INFO_MX7D_DDRC_P_OFFSET] ldrne r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] -- 2.17.1