From ac906764eec0d5e01fd0e91cb1c6af4b7e5955b3 Mon Sep 17 00:00:00 2001 From: Laurentiu Palcu Date: Wed, 7 Feb 2018 16:51:34 +0200 Subject: [PATCH] MLK-17634-11: drm: imx: dcss: make DCSS use VIDEO2_PLL2 clock This clock is needed by HDR10 so this patch makes DCSS use VIDEO2_PLL2 for the rest of the resolutions as well. Signed-off-by: Laurentiu Palcu --- drivers/gpu/imx/dcss/dcss-blkctl.c | 9 ++------- drivers/gpu/imx/dcss/dcss-common.c | 9 ++++++--- drivers/gpu/imx/dcss/dcss-dtg.c | 8 +++++--- drivers/gpu/imx/dcss/dcss-prv.h | 3 ++- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/imx/dcss/dcss-blkctl.c b/drivers/gpu/imx/dcss/dcss-blkctl.c index 2d6c94302242..168717797e51 100644 --- a/drivers/gpu/imx/dcss/dcss-blkctl.c +++ b/drivers/gpu/imx/dcss/dcss-blkctl.c @@ -81,13 +81,8 @@ void dcss_blkctl_cfg(struct dcss_soc *dcss) { struct dcss_blkctl_priv *blkctl = dcss->blkctl_priv; - if (blkctl->hdmi_output) - dcss_writel(blkctl->clk_setting, - blkctl->base_reg + DCSS_BLKCTL_CONTROL0); - else - dcss_writel((blkctl->clk_setting ^ HDMI_MIPI_CLK_SEL) | - DISPMIX_PIXCLK_SEL, - blkctl->base_reg + DCSS_BLKCTL_CONTROL0); + dcss_writel((blkctl->clk_setting ^ HDMI_MIPI_CLK_SEL), + blkctl->base_reg + DCSS_BLKCTL_CONTROL0); /* deassert clock domains resets */ dcss_blkctl_clk_reset(blkctl, 0, 0xffffff); diff --git a/drivers/gpu/imx/dcss/dcss-common.c b/drivers/gpu/imx/dcss/dcss-common.c index 24738c01f4a6..757c5b9b729f 100644 --- a/drivers/gpu/imx/dcss/dcss-common.c +++ b/drivers/gpu/imx/dcss/dcss-common.c @@ -272,7 +272,8 @@ static int dcss_clks_init(struct dcss_soc *dcss) } clks[] = { {"apb", &dcss->apb_clk}, {"axi", &dcss->axi_clk}, - {"pixel", &dcss->p_clk}, + {"pix_div", &dcss->pdiv_clk}, + {"pix_out", &dcss->pout_clk}, {"rtrm", &dcss->apb_clk}, {"dtrc", &dcss->dtrc_clk}, }; @@ -307,11 +308,13 @@ static void dcss_clocks_enable(struct dcss_soc *dcss, bool en) clk_prepare_enable(dcss->apb_clk); clk_prepare_enable(dcss->rtrm_clk); clk_prepare_enable(dcss->dtrc_clk); - clk_prepare_enable(dcss->p_clk); + clk_prepare_enable(dcss->pdiv_clk); + clk_prepare_enable(dcss->pout_clk); } if (!en && dcss->clks_on) { - clk_disable_unprepare(dcss->p_clk); + clk_disable_unprepare(dcss->pout_clk); + clk_disable_unprepare(dcss->pdiv_clk); clk_disable_unprepare(dcss->dtrc_clk); clk_disable_unprepare(dcss->rtrm_clk); clk_disable_unprepare(dcss->apb_clk); diff --git a/drivers/gpu/imx/dcss/dcss-dtg.c b/drivers/gpu/imx/dcss/dcss-dtg.c index 1c2ad8f7dfd0..dd8084a422ee 100644 --- a/drivers/gpu/imx/dcss/dcss-dtg.c +++ b/drivers/gpu/imx/dcss/dcss-dtg.c @@ -236,9 +236,11 @@ void dcss_dtg_sync_set(struct dcss_soc *dcss, struct videomode *vm) dis_lrc_y = vm->vsync_len + vm->vfront_porch + vm->vback_porch + vm->vactive - 1; - clk_disable_unprepare(dcss->p_clk); - clk_set_rate(dcss->p_clk, vm->pixelclock); - clk_prepare_enable(dcss->p_clk); + clk_disable_unprepare(dcss->pout_clk); + clk_disable_unprepare(dcss->pdiv_clk); + clk_set_rate(dcss->pdiv_clk, vm->pixelclock); + clk_prepare_enable(dcss->pdiv_clk); + clk_prepare_enable(dcss->pout_clk); dcss_dtg_write(dtg, ((dtg_lrc_y << TC_Y_POS) | dtg_lrc_x), DCSS_DTG_TC_DTG); diff --git a/drivers/gpu/imx/dcss/dcss-prv.h b/drivers/gpu/imx/dcss/dcss-prv.h index 8c349bf75532..ae9551a8953f 100644 --- a/drivers/gpu/imx/dcss/dcss-prv.h +++ b/drivers/gpu/imx/dcss/dcss-prv.h @@ -50,7 +50,8 @@ struct dcss_soc { struct clk *apb_clk; struct clk *axi_clk; - struct clk *p_clk; + struct clk *pdiv_clk; + struct clk *pout_clk; struct clk *rtrm_clk; struct clk *dtrc_clk; -- 2.17.1