From aab0c3fc8bd6680924573bab020e61301b7d0a2e Mon Sep 17 00:00:00 2001 From: Viorel Suman Date: Fri, 18 Aug 2017 12:09:14 +0300 Subject: [PATCH] MLK-13975-1: ASoC: fsl: qxp: Assign audio clocks within it's own power domain The patch mirrors commit f154ceffe411 ("MLK-13975: ASoC: fsl: Assign audio clocks within it's own power domain") for QXP. Signed-off-by: Viorel Suman --- .../dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts | 26 +++++++++++-------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts index b9d9d98b1add..08e49916c64e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts @@ -98,11 +98,10 @@ }; &acm { - assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + status = "okay"; +}; - assigned-clock-rates = <786432000>, <24576000>, <24576000>; +&amix { status = "okay"; }; @@ -121,22 +120,24 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esai0>; assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <24576000>; + assigned-clock-rates = <0>, <786432000>, <24576000>, <24576000>, <24576000>; dmas = <&edma2 23 0 3>, <&edma2 21 0 2>; status = "okay"; }; -&amix { - status = "okay"; -}; - &sai4 { assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QXP_AUD_SAI_4_MCLK>; assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <24576000>; + assigned-clock-rates = <0>, <786432000>, <24576000>, <24576000>, <24576000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; @@ -144,9 +145,12 @@ &sai5 { assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QXP_AUD_SAI_5_MCLK>; assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <24576000>; + assigned-clock-rates = <0>, <786432000>, <24576000>, <24576000>, <24576000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; -- 2.17.1