From a3a3170a96380eaaa70bc750c6048716075f84eb Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 3 Dec 2019 20:27:00 +0800 Subject: [PATCH] LF-95-3 arm64: imx8qxp-ss-lvds.dtsi: Correct LVDS/MIPI DSI region address and size The LVDS/MIPI DSI region is the CSR(Control Status Registers) space. The spec tells us that the CSR start address is 0x1000 and end address is 0x1FFF according to the subsystem start address. However, it turns out some space are inaccessible, which would accidently cause system hang via kernel regmap debugfs. This patch corrects the LVDS/MIPI DSI region start address and chooses a sensible size, which makes sure all exposed registers are accessible. Reviewed-by: Sandor Yu Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi index af6338e30c4e..b1d7b9c5ac82 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -104,9 +104,9 @@ power-domains = <&pd IMX_SC_R_MIPI_0>; }; - lvds_region1: lvds_region@56220000 { + lvds_region1: lvds_region@56221000 { compatible = "syscon"; - reg = <0x56220000 0x10000>; + reg = <0x56221000 0xf0>; }; ldb1_phy: ldb_phy@56221000 { @@ -266,9 +266,9 @@ power-domains = <&pd IMX_SC_R_MIPI_1>; }; - lvds_region2: lvds_region@56240000 { + lvds_region2: lvds_region@56241000 { compatible = "syscon"; - reg = <0x56240000 0x10000>; + reg = <0x56241000 0xf0>; }; ldb2_phy: ldb_phy@56241000 { -- 2.17.1