From a0a502622f42d7f15fa2f8f895798e471d7c733f Mon Sep 17 00:00:00 2001 From: Yuchou Gan Date: Sat, 31 Mar 2018 01:45:52 +0800 Subject: [PATCH] MGS-3786 [#ccc] Cncrease the clock rate of GPU3D/GPU2D for 7ulp B0 board The gpu3d/2d clock rate for 7ulp B0 board is 400M, increase it Signed-off-by: yuchou gan (cherry picked from commit b51ae7e98ccfd9e25697d3e5b9795699917496ea) --- drivers/clk/imx/clk-imx7ulp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index a2853b5acd64..6eb9b8ffbfb4 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -208,7 +208,7 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node) imx_clk_set_parent(clks[IMX7ULP_CLK_GPU2D], clks[IMX7ULP_CLK_APLL_PFD2]); imx_clk_set_parent(clks[IMX7ULP_CLK_GPU3D], clks[IMX7ULP_CLK_APLL_PFD2]); - imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 350000000); + imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD2], 400000000); /* setting the rate for emmc/sd usage */ imx_clk_set_rate(clks[IMX7ULP_CLK_APLL_PFD1], 352800000); -- 2.17.1