From 9f0fcbba9bd56decca4169ec9f1ebe2c246e947c Mon Sep 17 00:00:00 2001 From: Chenyan Feng Date: Mon, 31 Jul 2017 15:22:00 +0800 Subject: [PATCH] MGS-3145 gpu: dts: update GPU clock parent on i.MX8MQ Referred to the mscale design document, GPU has the designated clock PLL targeting for 800MHz, update the assigned-clk-parent to GPU_PLL_OUT in GPU device tree, fsl-imx8mq.dtsi. Signed-off-by: Chenyan Feng --- arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi index 9adda1babd5d..bfbf4ef696e0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi @@ -775,7 +775,7 @@ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI_DIV>, <&clk IMX8MQ_CLK_GPU_AHB_DIV>; clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI_SRC>, <&clk IMX8MQ_CLK_GPU_AHB_SRC>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>; assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; power-domains = <&power 4>; status = "disabled"; -- 2.17.1