From 9b048fab1126212ad0cb1a941cdb662d3f02c830 Mon Sep 17 00:00:00 2001 From: Oliver Brown Date: Tue, 8 Jan 2019 16:42:01 -0600 Subject: [PATCH] MLK-20707 gpu: imx: dcss: Change the pixel clock reference at runtime The clock referenece for the video pll 2 needs to be changed at runtime. The HDMI/DP PHY reference clock is not available during module initialization so the reference clock should be changed when the mode is set. Signed-off-by: Oliver Brown --- drivers/gpu/imx/dcss/dcss-common.c | 6 ++++++ drivers/gpu/imx/dcss/dcss-dtg.c | 7 +++++++ drivers/gpu/imx/dcss/dcss-prv.h | 2 ++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/imx/dcss/dcss-common.c b/drivers/gpu/imx/dcss/dcss-common.c index c2b916076ff4..639cc9176b8b 100644 --- a/drivers/gpu/imx/dcss/dcss-common.c +++ b/drivers/gpu/imx/dcss/dcss-common.c @@ -278,6 +278,8 @@ static int dcss_clks_init(struct dcss_soc *dcss) {"pix_out", &dcss->pout_clk}, {"rtrm", &dcss->rtrm_clk}, {"dtrc", &dcss->dtrc_clk}, + {"pll_src", &dcss->pll_src_clk}, + {"pll_phy_ref", &dcss->pll_phy_ref_clk}, }; for (i = 0; i < ARRAY_SIZE(clks); i++) { @@ -306,6 +308,8 @@ err: static void dcss_clocks_enable(struct dcss_soc *dcss, bool en) { if (en && !dcss->clks_on) { + clk_prepare_enable(dcss->pll_phy_ref_clk); + clk_prepare_enable(dcss->pll_src_clk); clk_prepare_enable(dcss->axi_clk); clk_prepare_enable(dcss->apb_clk); clk_prepare_enable(dcss->rtrm_clk); @@ -321,6 +325,8 @@ static void dcss_clocks_enable(struct dcss_soc *dcss, bool en) clk_disable_unprepare(dcss->rtrm_clk); clk_disable_unprepare(dcss->apb_clk); clk_disable_unprepare(dcss->axi_clk); + clk_disable_unprepare(dcss->pll_src_clk); + clk_disable_unprepare(dcss->pll_phy_ref_clk); } dcss->clks_on = en; diff --git a/drivers/gpu/imx/dcss/dcss-dtg.c b/drivers/gpu/imx/dcss/dcss-dtg.c index 3505fa1a8016..d32050b5dedf 100644 --- a/drivers/gpu/imx/dcss/dcss-dtg.c +++ b/drivers/gpu/imx/dcss/dcss-dtg.c @@ -298,8 +298,15 @@ void dcss_dtg_sync_set(struct dcss_soc *dcss, struct videomode *vm) vm->vactive - 1; if (dtg->hdmi_output) { + int err; clk_disable_unprepare(dcss->pout_clk); + clk_disable_unprepare(dcss->pll_src_clk); + err = clk_set_parent(dcss->pll_src_clk, dcss->pll_phy_ref_clk); + if (err < 0) + dev_warn(dcss->dev, "clk_set_parent() returned %d", + err); clk_set_rate(dcss->pout_clk, vm->pixelclock); + clk_prepare_enable(dcss->pll_src_clk); clk_prepare_enable(dcss->pout_clk); } else { clk_disable_unprepare(dcss->pout_clk); diff --git a/drivers/gpu/imx/dcss/dcss-prv.h b/drivers/gpu/imx/dcss/dcss-prv.h index 35ec541f2059..efab4b254200 100644 --- a/drivers/gpu/imx/dcss/dcss-prv.h +++ b/drivers/gpu/imx/dcss/dcss-prv.h @@ -69,6 +69,8 @@ struct dcss_soc { struct clk *pout_clk; struct clk *rtrm_clk; struct clk *dtrc_clk; + struct clk *pll_src_clk; + struct clk *pll_phy_ref_clk; void (*dcss_disable_callback)(void *data); -- 2.17.1