From 96f68c478549990c2c79e9afc3bf691e1fa90438 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 9 Apr 2021 23:06:46 -0700 Subject: [PATCH] LF-3483-13 imx8: Update SCFW API to version 1.16 Upgrade SCFW API to 1.16 to align with commit 8f2a1e1(SSI-87: imx8: Configure SNVS) in imx_v2020.04 u-boot. Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx8/sci/rpc.h | 34 ++++--- arch/arm/include/asm/arch-imx8/sci/sci.h | 18 +++- .../include/asm/arch-imx8/sci/svc/irq/api.h | 91 +++++++++++++++++++ .../include/asm/arch-imx8/sci/svc/misc/api.h | 42 ++++++--- .../include/asm/arch-imx8/sci/svc/pm/api.h | 82 +++++++++++++++++ .../include/asm/arch-imx8/sci/svc/rm/api.h | 14 ++- .../include/asm/arch-imx8/sci/svc/seco/api.h | 5 +- .../include/asm/arch-imx8/sci/svc/timer/api.h | 34 +++++++ arch/arm/include/asm/arch-imx8/sci/types.h | 18 +++- drivers/misc/imx8/scu_api.c | 22 +++++ include/dt-bindings/soc/imx_rsrc.h | 40 ++++---- 11 files changed, 339 insertions(+), 61 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 9f55904f44..5d28943538 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -11,7 +11,7 @@ /* Defines */ #define SCFW_API_VERSION_MAJOR 1U -#define SCFW_API_VERSION_MINOR 15U +#define SCFW_API_VERSION_MINOR 16U #define SC_RPC_VERSION 1U @@ -22,13 +22,13 @@ #define RPC_SVC(MSG) ((MSG)->svc) #define RPC_FUNC(MSG) ((MSG)->func) #define RPC_R8(MSG) ((MSG)->func) -#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (s64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) \ + | (s64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) #define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) #define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) -#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (u64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) \ + | (u64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) #define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) #define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) @@ -67,7 +67,9 @@ struct sc_rpc_msg_s { #define PM_FUNC_SET_SYS_POWER_MODE 19U #define PM_FUNC_SET_PARTITION_POWER_MODE 1U #define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_PARTITION_WAKE 28U #define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U #define PM_FUNC_GET_RESOURCE_POWER_MODE 4U #define PM_FUNC_REQ_LOW_POWER_MODE 16U #define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U @@ -81,12 +83,15 @@ struct sc_rpc_msg_s { #define PM_FUNC_GET_CLOCK_PARENT 15U #define PM_FUNC_RESET 13U #define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_GET_RESET_PART 26U #define PM_FUNC_BOOT 8U +#define PM_FUNC_SET_BOOT_PARM 27U #define PM_FUNC_REBOOT 9U #define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_REBOOT_CONTINUE 25U #define PM_FUNC_CPU_START 11U -#define PM_FUNC_CPU_RESET 23U -#define PM_FUNC_RESOURCE_RESET 29U +#define PM_FUNC_CPU_RESET 23U +#define PM_FUNC_RESOURCE_RESET 29U #define PM_FUNC_IS_PARTITION_STARTED 24U /* MISC RPC */ @@ -95,16 +100,10 @@ struct sc_rpc_msg_s { #define MISC_FUNC_GET_CONTROL 2U #define MISC_FUNC_SET_MAX_DMA_GROUP 4U #define MISC_FUNC_SET_DMA_GROUP 5U -#define MISC_FUNC_SECO_IMAGE_LOAD 8U -#define MISC_FUNC_SECO_AUTHENTICATE 9U -#define MISC_FUNC_SECO_FUSE_WRITE 20U -#define MISC_FUNC_SECO_ENABLE_DEBUG 21U -#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U -#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U -#define MISC_FUNC_SECO_BUILD_INFO 24U #define MISC_FUNC_DEBUG_OUT 10U #define MISC_FUNC_WAVEFORM_CAPTURE 6U #define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_API_VER 35U #define MISC_FUNC_UNIQUE_ID 19U #define MISC_FUNC_SET_ARI 3U #define MISC_FUNC_BOOT_STATUS 7U @@ -114,8 +113,11 @@ struct sc_rpc_msg_s { #define MISC_FUNC_SET_TEMP 12U #define MISC_FUNC_GET_TEMP 13U #define MISC_FUNC_GET_BOOT_DEV 16U -#define MISC_FUNC_GET_BUTTON_STATUS 18U +#define MISC_FUNC_GET_BOOT_TYPE 33U #define MISC_FUNC_GET_BOOT_CONTAINER 36U +#define MISC_FUNC_GET_BUTTON_STATUS 18U +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U +#define MISC_FUNC_BOARD_IOCTL 34U /* PAD RPC */ #define PAD_FUNC_UNKNOWN 0 @@ -160,6 +162,7 @@ struct sc_rpc_msg_s { #define RM_FUNC_GET_RESOURCE_INFO 16U #define RM_FUNC_MEMREG_ALLOC 17U #define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FRAG 32U #define RM_FUNC_MEMREG_FREE 18U #define RM_FUNC_FIND_MEMREG 30U #define RM_FUNC_ASSIGN_MEMREG 19U @@ -210,6 +213,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */ #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 1c29209b39..ad57455927 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -116,6 +118,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); /* SMMU API */ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); +/* Timer API */ +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); + /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr); @@ -126,13 +131,16 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, sc_faddr_t export_addr, u16 max_size); -int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size); -int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock); +int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + u16 dst_size); +int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + u8 size, u8 lock); int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, u16 msg_size, sc_faddr_t dst_addr, u16 dst_size); -int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, - u32 *data0, u32 *data1, u32 *data2, u32 *data3, - u32 *data4, u8 size); + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size); +int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, + u32 *data); #endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h new file mode 100644 index 0000000000..f701e60133 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef SC_IRQ_API_H +#define SC_IRQ_API_H + +/* Defines */ + +#define SC_IRQ_NUM_GROUP 7U /* Number of groups */ + +/* Defines for sc_irq_group_t */ +#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */ +#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */ +#define SC_IRQ_GROUP_REBOOTED 5U /* Partition reboot complete */ +#define SC_IRQ_GROUP_REBOOT 6U /* Partition reboot starting */ + +/* Defines for sc_irq_temp_t */ +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */ + +/* Defines for sc_irq_wdog_t */ +#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */ + +/* Defines for sc_irq_rtc_t */ +#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */ + +/* Defines for sc_irq_wake_t */ +#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */ +#define SC_IRQ_USR1 (1U << 2U) /* User defined 1 */ +#define SC_IRQ_USR2 (1U << 3U) /* User defined 2 */ +#define SC_IRQ_BC_PAD (1U << 4U) /* Pad wakeup (broadcast to all partitions) */ +#define SC_IRQ_SW_WAKE (1U << 5U) /* Software requested wake */ +#define SC_IRQ_SECVIO (1U << 6U) /* Security violation */ + +/* Defines for sc_irq_sysctr_t */ +#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */ + +/* Types */ + +/* + * This type is used to declare an interrupt group. + */ +typedef u8 sc_irq_group_t; + +/* + * This type is used to declare a bit mask of temp interrupts. + */ +typedef u8 sc_irq_temp_t; + +/* + * This type is used to declare a bit mask of watchdog interrupts. + */ +typedef u8 sc_irq_wdog_t; + +/* + * This type is used to declare a bit mask of RTC interrupts. + */ +typedef u8 sc_irq_rtc_t; + +/* + * This type is used to declare a bit mask of wakeup interrupts. + */ +typedef u8 sc_irq_wake_t; + +#endif /* SC_IRQ_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h index 3629eb68d7..a4b92b86cc 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -5,27 +5,45 @@ #ifndef SC_MISC_API_H #define SC_MISC_API_H +/* Defines for type widths */ +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */ +/* Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U /* Defines for sc_misc_boot_status_t */ #define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ #define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ - /* Defines for sc_misc_temp_t */ -#define SC_MISC_TEMP 0U /* Temp sensor */ -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_bt_t */ +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /* Serial boot */ +/* Types */ -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ -#define SC_MISC_REL_CONTAINER 2U /* Release container */ +/* + * This type is used to store a DMA channel priority group. + */ +typedef u8 sc_misc_dma_group_t; +/* + * This type is used report boot status. + */ typedef u8 sc_misc_boot_status_t; + +/* + * This type is used report boot status. + */ typedef u8 sc_misc_temp_t; +/* + * This type is used report the boot type. + */ +typedef u8 sc_misc_bt_t; #endif /* SC_MISC_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h index 109ec2781c..95956d74ff 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h @@ -6,6 +6,14 @@ #ifndef SC_PM_API_H #define SC_PM_API_H +#include +/* Defines for type widths */ +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ +/* Defines for ALL parameters */ +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */ /* Defines for sc_pm_power_mode_t */ #define SC_PM_PW_MODE_OFF 0U /* Power off */ #define SC_PM_PW_MODE_STBY 1U /* Power in standby */ @@ -42,10 +50,84 @@ #define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ #define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ +/* Defines for sc_pm_reset_type_t */ +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ + +/* Defines for sc_pm_reset_reason_t */ +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ + +/* Defines for sc_pm_sys_if_t */ +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ + +/* Defines for sc_pm_wake_src_t */ +#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */ +/* Types */ + +/* + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ typedef u8 sc_pm_power_mode_t; + +/* + * This type is used to declare a clock. + */ typedef u8 sc_pm_clk_t; + +/* + * This type is used to declare a clock mode. + */ typedef u8 sc_pm_clk_mode_t; + +/* + * This type is used to declare the clock parent. + */ typedef u8 sc_pm_clk_parent_t; + +/* + * This type is used to declare clock rates. + */ typedef u32 sc_pm_clock_rate_t; +/* + * This type is used to declare a desired reset type. + */ +typedef u8 sc_pm_reset_type_t; + +/* + * This type is used to declare a reason for a reset. + */ +typedef u8 sc_pm_reset_reason_t; + +/* + * This type is used to specify a system-level interface to be power managed. + */ +typedef u8 sc_pm_sys_if_t; + +/* + * This type is used to specify a wake source for CPU resources. + */ +typedef u8 sc_pm_wake_src_t; #endif /* SC_PM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h index ed303881e7..bbc9de9016 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h @@ -38,32 +38,36 @@ /* Types */ -/*! +/* * This type is used to declare a resource partition. */ typedef u8 sc_rm_pt_t; -/*! +/* * This type is used to declare a memory region. */ typedef u8 sc_rm_mr_t; -/*! +/* * This type is used to declare a resource domain ID used by the * isolation HW. */ typedef u8 sc_rm_did_t; -/*! +/* * This type is used to declare an SMMU StreamID. */ typedef u16 sc_rm_sid_t; -/*! +/* * This type is a used to declare master transaction attributes. */ typedef u8 sc_rm_spa_t; +/* + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ typedef u8 sc_rm_perm_t; #endif /* SC_RM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h index 3ed05842d9..5963330d3a 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h @@ -17,6 +17,7 @@ #define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ #define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ #define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */ #define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ #define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ @@ -24,12 +25,12 @@ /* Types */ -/*! +/* * This type is used to issue SECO authenticate commands. */ typedef u8 sc_seco_auth_cmd_t; -/*! +/* * This type is used to return the RNG initialization status. */ typedef u32 sc_seco_rng_stat_t; diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h new file mode 100644 index 0000000000..d5750444b3 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Defines */ + +/* Defines for type widths */ +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ + +/* Defines for sc_timer_wdog_action_t */ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ + +/* Types */ + +/* + * This type is used to configure the watchdog action. + */ +typedef u8 sc_timer_wdog_action_t; + +/* + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef u32 sc_timer_wdog_time_t; + +#endif /* SC_TIMER_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h index 8a70af2998..a5c00c3c39 100644 --- a/arch/arm/include/asm/arch-imx8/sci/types.h +++ b/arch/arm/include/asm/arch-imx8/sci/types.h @@ -19,6 +19,7 @@ typedef u64 sc_ipc_t; /* Defines for common frequencies */ #define SC_32KHZ 32768U /* 32KHz */ #define SC_10MHZ 10000000U /* 10MHz */ +#define SC_16MHZ 16000000U /* 16MHz */ #define SC_20MHZ 20000000U /* 20MHz */ #define SC_25MHZ 25000000U /* 25MHz */ #define SC_27MHZ 27000000U /* 27MHz */ @@ -58,21 +59,33 @@ typedef u64 sc_ipc_t; #define SC_594MHZ 594000000U /* 594MHz */ #define SC_625MHZ 625000000U /* 625MHz */ #define SC_640MHZ 640000000U /* 640MHz */ +#define SC_648MHZ 648000000U /* 648MHz */ #define SC_650MHZ 650000000U /* 650MHz */ #define SC_667MHZ 666666667U /* 667MHz */ #define SC_675MHZ 675000000U /* 675MHz */ #define SC_700MHZ 700000000U /* 700MHz */ #define SC_720MHZ 720000000U /* 720MHz */ #define SC_750MHZ 750000000U /* 750MHz */ +#define SC_753MHZ 753000000U /* 753MHz */ +#define SC_793MHZ 793000000U /* 793MHz */ #define SC_800MHZ 800000000U /* 800MHz */ #define SC_850MHZ 850000000U /* 850MHz */ +#define SC_858MHZ 858000000U /* 858MHz */ #define SC_900MHZ 900000000U /* 900MHz */ +#define SC_953MHZ 953000000U /* 953MHz */ +#define SC_963MHZ 963000000U /* 963MHz */ #define SC_1000MHZ 1000000000U /* 1GHz */ #define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1068MHZ 1068000000U /* 1.068GHz */ +#define SC_1121MHZ 1121000000U /* 1.121GHz */ +#define SC_1173MHZ 1173000000U /* 1.173GHz */ #define SC_1188MHZ 1188000000U /* 1.188GHz */ #define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1278MHZ 1278000000U /* 1.278GHz */ #define SC_1280MHZ 1280000000U /* 1.28GHz */ #define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1313MHZ 1313000000U /* 1.313GHz */ +#define SC_1345MHZ 1345000000U /* 1.345GHz */ #define SC_1400MHZ 1400000000U /* 1.4GHz */ #define SC_1500MHZ 1500000000U /* 1.5GHz */ #define SC_1600MHZ 1600000000U /* 1.6GHz */ @@ -119,7 +132,6 @@ typedef u64 sc_ipc_t; #define SC_755MHZ 755250000U /* 755.25MHz */ /* Defines for type widths */ -#define SC_FADDR_W 36U /* Width of sc_faddr_t */ #define SC_BOOL_W 1U /* Width of sc_bool_t */ #define SC_ERR_W 4U /* Width of sc_err_t */ #define SC_RSRC_W 10U /* Width of sc_rsrc_t */ @@ -201,7 +213,9 @@ typedef u64 sc_ipc_t; #define SC_C_IPG_STOP_MODE 53U #define SC_C_IPG_STOP_ACK 54U #define SC_C_SYNC_CTRL 55U -#define SC_C_LAST 56U +#define SC_C_OFS_AUDIO_ALT 56U +#define SC_C_DSP_BYP 57U +#define SC_C_LAST 58U #define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 27ecce710f..f813d54284 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -877,6 +877,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, return ret; } +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = (u8)(TIMER_FUNC_SET_WDOG_WINDOW); + + RPC_U32(&msg, 0U) = (u32)(window); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: window:%u: res:%d\n", + __func__, window, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h index 16305779e0..da4b7b8879 100644 --- a/include/dt-bindings/soc/imx_rsrc.h +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -35,14 +35,14 @@ #define SC_R_DC_0_BLIT2 21 #define SC_R_DC_0_BLIT_OUT 22 #define SC_R_PERF 23 -#define SC_R_UNUSED5 24 +#define SC_R_USB_1_PHY 24 #define SC_R_DC_0_WARP 25 -#define SC_R_UNUSED7 26 -#define SC_R_UNUSED8 27 +#define SC_R_V2X_MU_0 26 +#define SC_R_V2X_MU_1 27 #define SC_R_DC_0_VIDEO0 28 #define SC_R_DC_0_VIDEO1 29 #define SC_R_DC_0_FRAC0 30 -#define SC_R_UNUSED6 31 +#define SC_R_V2X_MU_2 31 #define SC_R_DC_0 32 #define SC_R_GPU_2_PID0 33 #define SC_R_DC_0_PLL_0 34 @@ -51,11 +51,11 @@ #define SC_R_DC_1_BLIT1 37 #define SC_R_DC_1_BLIT2 38 #define SC_R_DC_1_BLIT_OUT 39 -#define SC_R_UNUSED9 40 -#define SC_R_UNUSED10 41 +#define SC_R_V2X_MU_3 40 +#define SC_R_V2X_MU_4 41 #define SC_R_DC_1_WARP 42 -#define SC_R_UNUSED11 43 -#define SC_R_UNUSED12 44 +#define SC_R_TBU_CTL 43 +#define SC_R_SECVIO 44 #define SC_R_DC_1_VIDEO0 45 #define SC_R_DC_1_VIDEO1 46 #define SC_R_DC_1_FRAC0 47 @@ -151,10 +151,10 @@ #define SC_R_DMA_1_CH29 137 #define SC_R_DMA_1_CH30 138 #define SC_R_DMA_1_CH31 139 -#define SC_R_UNUSED1 140 -#define SC_R_UNUSED2 141 -#define SC_R_UNUSED3 142 -#define SC_R_UNUSED4 143 +#define SC_R_V2X_PID0 140 +#define SC_R_V2X_PID1 141 +#define SC_R_V2X_PID2 142 +#define SC_R_V2X_PID3 143 #define SC_R_GPU_0_PID0 144 #define SC_R_GPU_0_PID1 145 #define SC_R_GPU_0_PID2 146 @@ -301,8 +301,8 @@ #define SC_R_M4_0_UART 287 #define SC_R_M4_0_I2C 288 #define SC_R_M4_0_INTMUX 289 -#define SC_R_UNUSED15 290 -#define SC_R_UNUSED16 291 +#define SC_R_ENET_0_A0 290 +#define SC_R_ENET_0_A1 291 #define SC_R_M4_0_MU_0B 292 #define SC_R_M4_0_MU_0A0 293 #define SC_R_M4_0_MU_0A1 294 @@ -377,12 +377,12 @@ #define SC_R_VPU_PID5 363 #define SC_R_VPU_PID6 364 #define SC_R_VPU_PID7 365 -#define SC_R_VPU_UART 366 -#define SC_R_VPUCORE 367 -#define SC_R_VPUCORE_0 368 -#define SC_R_VPUCORE_1 369 -#define SC_R_VPUCORE_2 370 -#define SC_R_VPUCORE_3 371 +#define SC_R_ENET_0_A2 366 +#define SC_R_ENET_1_A0 367 +#define SC_R_ENET_1_A1 368 +#define SC_R_ENET_1_A2 369 +#define SC_R_ENET_1_A3 370 +#define SC_R_ENET_1_A4 371 #define SC_R_DMA_4_CH0 372 #define SC_R_DMA_4_CH1 373 #define SC_R_DMA_4_CH2 374 -- 2.17.1