From 91e57b2a866770dcda9770389515df2c820902f5 Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Tue, 31 Oct 2023 13:36:35 +0100 Subject: [PATCH] =?utf8?q?arm64:=20dts:=20imx8mp-somdevices.dtsi:=20Set=20?= =?utf8?q?proper=20pins:=20=C2=B7=20Set=20proper=20pins=20to=20pwm,=20spi,?= =?utf8?q?=20pcie,=20uart,=20gpio,=20can=20and=20i2c.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Josep Orga --- .../boot/dts/freescale/imx8mp-somdevices.dtsi | 96 +++++++++++++++---- 1 file changed, 75 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi index a66d2934df1e..635117a839be 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi @@ -112,7 +112,7 @@ lvds_backlight: lvds_backlight { compatible = "pwm-backlight"; - pwms = <&pwm2 0 100000>; + pwms = <&pwm1 0 2000000>; status = "okay"; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 @@ -164,6 +164,12 @@ status = "okay"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &aud2htx { status = "disabled"; }; @@ -174,10 +180,10 @@ fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio1 13 GPIO_ACTIVE_LOW>; status = "okay"; - spidev1: spi@0 { + spidev0: spi@0 { reg = <0>; compatible = "rohm,dh2228fv"; spi-max-frequency = <500000>; @@ -352,7 +358,7 @@ }; &i2c2 { - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; @@ -365,6 +371,13 @@ status = "okay"; }; +&i2c5 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5>; + status = "okay"; +}; + &irqsteer_hdmi { status = "okay"; }; @@ -427,12 +440,12 @@ status = "disabled"; }; -&pcie{ +&pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; - ext_osc = <1>; + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + wake-up-gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + ext_osc = <0>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_HSIO_AXI>, @@ -447,10 +460,10 @@ status = "okay"; }; -&pcie_ep{ +&pcie_ep { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - ext_osc = <1>; + ext_osc = <0>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_HSIO_AXI>, @@ -464,8 +477,8 @@ status = "disabled"; }; -&pcie_phy{ - ext_osc = <1>; +&pcie_phy { + ext_osc = <0>; status = "okay"; }; @@ -533,6 +546,12 @@ status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usb3_phy0 { status = "okay"; }; @@ -630,6 +649,22 @@ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + + /* SOMDEVICES GPIOs */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19 //GPIO00 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 //GPIO01 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 //GPIO02 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 //GPIO03 + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 //GPIO04 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 //GPIO05 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x19 //GPIO06 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x19 //GPIO07 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19 //GPIO08 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x19 //GPIO09 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19 //GPIO10 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x19 //GPIO11 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x19 //GPIO12 + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x19 //GPIO13 >; }; @@ -639,6 +674,12 @@ >; }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116 + >; + }; + pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 @@ -650,6 +691,7 @@ pinctrl_ecspi2_cs: ecspi2cs { fsl,pins = < MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000 >; }; @@ -695,15 +737,15 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 >; }; @@ -715,6 +757,7 @@ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 /* QSPI_A_nSS1_GPIO */ >; }; @@ -745,12 +788,18 @@ >; }; + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 - MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x41 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x41 >; }; @@ -773,8 +822,6 @@ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 >; }; @@ -813,6 +860,13 @@ >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + pinctrl_usb1_vbus: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x19 -- 2.17.1