From 9101d44953a7d006aa1679662b000840eaba3dba Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Mon, 5 Jun 2017 10:53:07 +0800 Subject: [PATCH] MLK-15001-31 arm64: dtsi: fsl-imx8qm: Add LDB support This patch adds LDB support. Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 91ba28a84d82..769898357b95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -915,13 +915,20 @@ reg = <1>; dpu1_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb1_lvds0>; }; dpu1_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb1_lvds1>; }; }; }; + lvds_region1: lvds_region@56240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + ldb1_phy: ldb_phy@56241000 { #address-cells = <1>; #size-cells = <0>; @@ -943,6 +950,52 @@ }; }; + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, + <&clk IMX8QM_LVDS0_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds0>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds0: endpoint { + remote-endpoint = <&dpu1_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds1: endpoint { + remote-endpoint = <&dpu1_disp1_lvds1>; + }; + }; + }; + }; + dpu2_intsteer: dpu_intsteer@57000000 { compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; reg = <0x0 0x57000000 0x0 0x10000>; @@ -989,13 +1042,20 @@ reg = <1>; dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; }; dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; }; }; }; + lvds_region2: lvds_region@57240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x57240000 0x0 0x10000>; + }; + ldb2_phy: ldb_phy@57241000 { #address-cells = <1>; #size-cells = <0>; @@ -1017,6 +1077,52 @@ }; }; + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, + <&clk IMX8QM_LVDS1_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds1>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds0: endpoint { + remote-endpoint = <&dpu2_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds1: endpoint { + remote-endpoint = <&dpu2_disp1_lvds1>; + }; + }; + }; + }; + i2c0: i2c@5a800000 { compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x0 0x5a800000 0x0 0x4000>; -- 2.17.1