From 889fef962ab4b86944735b8e7d993ed93bbc57ec Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 29 Oct 2017 21:53:21 -0500 Subject: [PATCH] MLK-16724 imx8mq: clock: Fix FRAC PLL caculation issue According to the FRAC PLL formula, DIVF_VAL = 1 + DIVFI + (DIVFF/224). But in decode_frac_pll, the DIVFI and DIVFF are both added with 1. Fix it to align with the formula. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/cpu/armv8/imx8m/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/imx8m/clock.c b/arch/arm/cpu/armv8/imx8m/clock.c index 7e1ad66860..a121871192 100644 --- a/arch/arm/cpu/armv8/imx8m/clock.c +++ b/arch/arm/cpu/armv8/imx8m/clock.c @@ -82,7 +82,7 @@ u32 decode_frac_pll(enum clk_root_src frac_pll) FRAC_PLL_FRAC_DIV_CTL_SHIFT; divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; - divf_val = 1 + (divfi + 1) + (divff + 1) / (1 << 24); + divf_val = 1 + divfi + divff / (1 << 24); pllout = pll_refclk / (divr_val + 1) * 8 * divf_val / ((divq_val + 1) * 2); -- 2.17.1