From 879bf9f53bf10087ef882203e6e451245b197af5 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 4 May 2016 14:55:11 +0800 Subject: [PATCH] MLK-12757-1 ARM: dts: imx6ull-ddr3-arm2.dts: change usdhc2 pad setting According to Hardware team's suggestion, for usdhc2, this patch change the drive strength for clock pin and data pin, which can make the signal meet the requirement for DDR50 mode. Signed-off-by: Haibo Chen Signed-off-by: Arulpandiyan Vadivel Signed-off-by: Srikanth Krishnakar --- arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts index 2c35f41d1c14..96cf48a8f160 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts @@ -839,11 +839,11 @@ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9 >; }; -- 2.17.1