From 72e2c02d5b4e4c64ca4c809bcce27205da43a67c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 21 Jan 2018 19:22:40 -0800 Subject: [PATCH] MLK-17439 mx7ulp: Change clock rate calculation for NIC1 BUS and EXT On i.MX7ULP B0, there is change in NIC clock dividers architecture. On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but on B0 they are parallel with NIC1 DIV. So now the dividers are independent. This patch modifies the scg_nic_get_rate function according to this change. Signed-off-by: Ye Li Acked-by: Peng Fan (cherry picked from commit 1a53e025c6be73a84570a3857cb709d98e49ef96) (cherry picked from commit ae54e190e6085687658419c4d971ae51fe91c589) --- arch/arm/mach-imx/mx7ulp/scg.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 3bedeb4187..283752ba03 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -353,7 +353,7 @@ static u32 scg_ddr_get_rate(void) static u32 scg_nic_get_rate(enum scg_clk clk) { - u32 reg, val, rate; + u32 reg, val, rate, nic0_rate; u32 shift, mask; reg = readl(&scg1_regs->niccsr); @@ -371,6 +371,7 @@ static u32 scg_nic_get_rate(enum scg_clk clk) val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; rate = rate / (val + 1); + nic0_rate = rate; clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); @@ -412,6 +413,10 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return 0; } + /* On RevB, the nic_bus and nic_ext dividers are parallel not chained with nic div */ + if (soc_rev() >= CHIP_REV_2_0) + rate = nic0_rate; + val = (reg & mask) >> shift; rate = rate / (val + 1); -- 2.17.1