From 6f594a857b43829c8ab41212aaf4494538244735 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 8 Jun 2018 17:59:53 +0800 Subject: [PATCH] MLK-18578: hdmi_rx: fix issue that ARC can't work in 4k. After changing the deemphasis to 0dB in TX_DIG_CTRL_REG_1 the issue that ARC can't work with 4k resolution is fixed Signed-off-by: Shengjiu Wang Reviewed-by: Sandor.yu --- drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.c | 3 ++- drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.c b/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.c index d03b606d7809..7961b6a9acf8 100644 --- a/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.c +++ b/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.c @@ -97,6 +97,7 @@ void arc_config(state_struct *state) write16(state, TXDA_CYA_AUXDA_CYA_ADDR, 0x0001); + write16(state, TX_DIG_CTRL_REG_1_ADDR, 0x3); write16(state, TX_DIG_CTRL_REG_2_ADDR, 0x0024); reg_val = read16(state, TX_ANA_CTRL_REG_1_ADDR); @@ -110,7 +111,7 @@ void arc_config(state_struct *state) write16(state, TX_ANA_CTRL_REG_1_ADDR, 0x2018); write16(state, TX_ANA_CTRL_REG_1_ADDR, 0x2098); write16(state, TX_ANA_CTRL_REG_2_ADDR, 0x030C); - write16(state, TX_ANA_CTRL_REG_5_ADDR, 0x0000); + write16(state, TX_ANA_CTRL_REG_5_ADDR, 0x0010); write16(state, TX_ANA_CTRL_REG_4_ADDR, 0x4001); write16(state, TX_ANA_CTRL_REG_1_ADDR, 0x2198); write16(state, TX_ANA_CTRL_REG_2_ADDR, 0x030D); diff --git a/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.h b/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.h index 225e767d6356..14992f650f7f 100644 --- a/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.h +++ b/drivers/media/platform/imx8/hdmi/API_AFE_ss28fdsoi_hdmirx.h @@ -87,6 +87,7 @@ #define XCVR_DIAG_RX_LANE_CAL_RST_TMR_ADDR 0x40EA #define TX_ANA_CTRL_REG_1_ADDR 0x5020 #define TX_ANA_CTRL_REG_2_ADDR 0x5021 +#define TX_DIG_CTRL_REG_1_ADDR 0x5023 #define TX_DIG_CTRL_REG_2_ADDR 0x5024 #define TXDA_CYA_AUXDA_CYA_ADDR 0x5025 #define TX_ANA_CTRL_REG_3_ADDR 0x5026 -- 2.17.1