From 6e771295ce1b16df5f234d5ef9e807e9169c0507 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 22 Jul 2015 10:34:02 +0800 Subject: [PATCH] MLK-11265-1 ARM: dts: add imx7d soc dtsi support Add new SoC i.MX7D dtsi and pinfunc head file. Signed-off-by: Anson Huang --- arch/arm/boot/dts/imx7d.dtsi | 358 ++++++++++++++++++++++++ include/dt-bindings/clock/imx7d-clock.h | 4 +- 2 files changed, 361 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index f6dee41a05d9..d4a450e2fee2 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -83,6 +83,260 @@ }; }; }; + + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel", + "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + status = "disabled"; + }; + + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x00901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@00180000 { + compatible = "fsl,lpm-sram"; + reg = <0x00180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocrams_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, + <&clks IMX7D_NAND_ROOT_CLK>; + clock-names = "dma_apbh_bch", "dma_apbh_io"; + }; + + pcie: pcie@0x33800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + pcie-phy-supply = <®_1p0d>; + status = "disabled"; + }; + }; +}; + +&aips1 { + kpp: kpp@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + ocotp-fuse@30350000 { + compatible = "fsl,imx7d-ocotp"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_OCOTP_CLK>; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupts = ; + fsl,tempmon =<&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + }; +}; + +&anatop { + reg_1p2: regulator-vdd1p2@220 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <31>; + }; +}; + +&aips2 { + flextimer1: flextimer@30640000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30640000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + flextimer2: flextimer@30650000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30650000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = , + ; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "pxp-axi"; + status = "disabled"; + }; + + csi1: csi@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 1>; + bus-width = <4>; + status = "disabled"; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + mipi-phy-supply = <®_1p0d>; + status = "disabled"; + }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; }; }; @@ -127,6 +381,110 @@ fsl,num-rx-queues=<3>; status = "disabled"; }; + + crypto: caam@30900000 { + compatible = "fsl,imx7d-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "caam_ipg", "caam_aclk"; + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + mcctest: mcctest{ + compatible = "fsl,imx6sx-mcc-test"; + status = "disabled"; + }; + + mcctty: mcctty{ + compatible = "fsl,imx6sx-mcc-tty"; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + status = "disabled"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + qspi1: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + weim: weim@30bc0000 { + compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim"; + reg = <0x30bc0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_EIM_ROOT_CLK>; + status = "disabled"; + }; + +}; + +&usbphynop3 { + vcc-supply = <®_1p2>; }; &ca_funnel_ports { diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index 1183347c383f..f09e890f832d 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -449,5 +449,7 @@ #define IMX7D_ADC_ROOT_CLK 436 #define IMX7D_CLK_ARM 437 #define IMX7D_CKIL 438 -#define IMX7D_CLK_END 439 +#define IMX7D_OCOTP_CLK 439 +#define IMX7D_CAAM_CLK 440 +#define IMX7D_CLK_END 441 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ -- 2.17.1