From 6da4adaf0cd9a36503ec2686435de30c6e0af7bf Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 22 Aug 2018 22:04:22 -0700 Subject: [PATCH] MLK-19308 mx7d_lpddr3_arm2: Fix plugin boot failed issue The QOS relevant registers are not defined in register header file. When building plugin, these addresses are set to 0 and cause plugin failed. Move the QOS registers definitions from set_epdc_qos to register header file to fix the issue. Signed-off-by: Ye Li (cherry picked from commit 11b519b7805d1467cb4c35a5fa96f38da7d78497) --- arch/arm/include/asm/arch-mx7/imx-regs.h | 4 ++++ arch/arm/mach-imx/mx7/soc.c | 5 ----- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 6336514007..cf71e61c3d 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -212,6 +212,10 @@ #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 6bf4d5b7a3..8597c0c12c 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -268,11 +268,6 @@ static void imx_gpcv2_init(void) static void set_epdc_qos(void) { -#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR -#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) -#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) -#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) - writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */ writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */ writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */ -- 2.17.1