From 6a27630e6ef7b9490a9b03b5abae4f2d0babeeae Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Thu, 7 Sep 2023 12:04:44 +0200 Subject: [PATCH] imx8mp-somdevices: Enable ethernet. Signed-off-by: Josep Orga --- arch/arm/dts/imx8mp-somdevices.dts | 36 +++++++++-------------------- configs/imx8mp_somdevices_defconfig | 1 + include/configs/imx8mp_somdevices.h | 4 ++-- 3 files changed, 14 insertions(+), 27 deletions(-) diff --git a/arch/arm/dts/imx8mp-somdevices.dts b/arch/arm/dts/imx8mp-somdevices.dts index a357de1493..6c6056d1ed 100644 --- a/arch/arm/dts/imx8mp-somdevices.dts +++ b/arch/arm/dts/imx8mp-somdevices.dts @@ -113,6 +113,9 @@ pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; status = "okay"; mdio { @@ -120,9 +123,9 @@ #address-cells = <1>; #size-cells = <0>; - ethphy0: ethernet-phy@1 { + ethphy0: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; + reg = <4>; eee-broken-1000t; }; }; @@ -135,26 +138,6 @@ status = "okay"; }; -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - }; - }; -}; - &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -167,6 +150,9 @@ pinctrl-0 = <&pinctrl_fec>; phy-mode = "rgmii-id"; phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; fsl,magic-packet; status = "okay"; @@ -174,9 +160,9 @@ #address-cells = <1>; #size-cells = <0>; - ethphy1: ethernet-phy@1 { + ethphy1: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; + reg = <4>; eee-broken-1000t; }; }; @@ -470,7 +456,7 @@ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 >; }; diff --git a/configs/imx8mp_somdevices_defconfig b/configs/imx8mp_somdevices_defconfig index 6362bf01f1..3070cd3652 100644 --- a/configs/imx8mp_somdevices_defconfig +++ b/configs/imx8mp_somdevices_defconfig @@ -107,6 +107,7 @@ CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHY_REALTEK=y CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_DWC_ETH_QOS=y diff --git a/include/configs/imx8mp_somdevices.h b/include/configs/imx8mp_somdevices.h index 42d57fcc1a..1044a7cf3d 100644 --- a/include/configs/imx8mp_somdevices.h +++ b/include/configs/imx8mp_somdevices.h @@ -56,9 +56,9 @@ #define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_FEC_MXC_PHYADDR 4 -#define DWC_NET_PHYADDR 1 +#define DWC_NET_PHYADDR 4 #define PHY_ANEG_TIMEOUT 20000 -- 2.17.1