From 696326cba50890331370e18ef41a7f63293def8f Mon Sep 17 00:00:00 2001 From: Jian Li Date: Mon, 4 Dec 2017 10:30:46 +0800 Subject: [PATCH] MLK-17055 imx8mq: evk: update DDR seting for display flickering issue 1. With this change, no flickering when LCDIF + MIPI-DSI in 720p60 single display case 2. With this change, no flickering when DCSS in 4kp60 while running 4x memtester at the same time side effect: GPU resolve performance downgrade ~20%, no obvious impact to non-resolve GPU cases. Signed-off-by: Jian Li --- board/freescale/imx8mq_evk/ddr/ddr_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imx8mq_evk/ddr/ddr_init.c b/board/freescale/imx8mq_evk/ddr/ddr_init.c index 8572a6f1f3..ba46201209 100644 --- a/board/freescale/imx8mq_evk/ddr/ddr_init.c +++ b/board/freescale/imx8mq_evk/ddr/ddr_init.c @@ -90,7 +90,7 @@ void lpddr4_800MHz_cfg_umctl2(void) dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505); dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c); dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b); - dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x900093e7); + dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009); dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574); dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016); dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000); -- 2.17.1