From 68e64f1b5ab353561be980797ddc3061aa66555b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 7 Feb 2017 10:22:02 +0800 Subject: [PATCH] MLK-14418-8 imx: mx7dsabresd: add epdc support Add epdc support from v2019.04. Add a epdc specified DTS file for using epdc Signed-off-by: Peng Fan Signed-off-by: Ye Li (cherry picked from commit ab2f9e136f5da034a8335dc8ca276a54367132e8) (cherry picked from commit ccfa28aec4093ac30a9b76d973f0288ab9c8f92c) (cherry picked from commit 86f7a2c50aeb4d5c12f7159356ea782f48905b19) (cherry picked from commit 77e171129baef32ec836f51afc18be89421d5512) --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx7d-sdb-epdc.dts | 62 +++++ board/freescale/mx7dsabresd/mx7dsabresd.c | 292 ++++++++++++++++++++++ configs/mx7dsabresd_epdc_defconfig | 98 ++++++++ include/configs/mx7dsabresd.h | 20 ++ 5 files changed, 473 insertions(+) create mode 100644 arch/arm/dts/imx7d-sdb-epdc.dts create mode 100644 configs/mx7dsabresd_epdc_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6cb3972153..651eaa2610 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -772,6 +772,7 @@ dtb-$(CONFIG_ARCH_MX6) += \ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ + imx7d-sdb-epdc.dtb \ imx7d-sdb-gpmi-weim.dtb \ imx7d-sdb-reva.dtb \ imx7-colibri-emmc.dtb \ diff --git a/arch/arm/dts/imx7d-sdb-epdc.dts b/arch/arm/dts/imx7d-sdb-epdc.dts new file mode 100644 index 0000000000..8183a25414 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-epdc.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + */ + +#include "imx7d-sdb.dts" + +&epdc { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +®_fec2_3v3 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; + +&sii902x { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; + +&uart5 { + status = "disabled"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio6 13 0>; + gpio_elan_rst = <&gpio6 15 0>; + gpio_intr = <&gpio6 12 0>; + status = "okay"; + }; +}; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 5c65986a2d..de7c4daecb 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -27,6 +27,10 @@ #include #include #include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif #include DECLARE_GLOBAL_DATA_PTR; @@ -44,6 +48,8 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) +#define EPDC_PAD_CTRL 0x0 + #ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi3_pads[] = { MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -315,6 +321,263 @@ int board_qspi_init(void) } #endif +#ifdef CONFIG_MXC_EPDC +iomux_v3_cfg_t const epdc_en_pads[] = { + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +struct gpio_desc epd_pwrstat_desc; +struct gpio_desc epd_vcom_desc; +struct gpio_desc epd_wakeup_desc; +struct gpio_desc epd_pwr_ctl0_desc; + +static void setup_epdc_power(void) +{ + int ret; + + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + ret = dm_gpio_lookup_name("GPIO2_31", &epd_pwrstat_desc); + if (ret) { + printf("%s lookup GPIO2_31 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_pwrstat_desc, "epdc_pwrstat"); + if (ret) { + printf("%s request epdc_pwrstat failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO4_14", &epd_vcom_desc); + if (ret) { + printf("%s lookup GPIO4_14 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_vcom_desc, "epdc_vcom"); + if (ret) { + printf("%s request epdc_vcom failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO2_23", &epd_wakeup_desc); + if (ret) { + printf("%s lookup GPIO2_23 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_wakeup_desc, "epdc_pmic"); + if (ret) { + printf("%s request epdc_pmic failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO2_30", &epd_pwr_ctl0_desc); + if (ret) { + printf("%s lookup GPIO2_30 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_pwr_ctl0_desc, "epdc_pwr_ctl0"); + if (ret) { + printf("%s request epdc_pwr_ctl0 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + dm_gpio_set_value(&epd_pwr_ctl0_desc, 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + dm_gpio_set_value(&epd_wakeup_desc, 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + dm_gpio_set_value(&epd_vcom_desc, 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + dm_gpio_set_value(&epd_wakeup_desc, 0); + + /* Disable VCOM */ + dm_gpio_set_value(&epd_vcom_desc, 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + dm_gpio_set_value(&epd_pwr_ctl0_desc, 0); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -339,6 +602,35 @@ int board_init(void) board_qspi_init(); #endif +#ifdef CONFIG_MXC_EPDC + if (mx7sabre_rev() >= BOARD_REV_B) { + int ret; + struct gpio_desc desc; + /* + * From RevB, GPIO1_IO04 is used for ENET2 EN, + * so set its output to high to isolate the + * ENET2 signals for EPDC + */ + imx_iomux_v3_setup_multiple_pads(epdc_en_pads, + ARRAY_SIZE(epdc_en_pads)); + + ret = dm_gpio_lookup_name("GPIO1_4", &desc); + if (ret) { + printf("%s lookup GPIO1_4 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&desc, "epdc_en"); + if (ret) { + printf("%s request epdc_en failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + setup_epdc(); +#endif + #ifdef CONFIG_MXC_SPI setup_spi(); #endif diff --git a/configs/mx7dsabresd_epdc_defconfig b/configs/mx7dsabresd_epdc_defconfig new file mode 100644 index 0000000000..562fc348ab --- /dev/null +++ b/configs/mx7dsabresd_epdc_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_CMD_BMP=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-epdc" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 528e4c70a0..e763ed6d89 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -249,4 +249,24 @@ #define CONFIG_IMX_VIDEO_SKIP #endif +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" +#endif + #endif /* __CONFIG_H */ -- 2.17.1