From 5ffc689a3ec941f99fef5d77cdb94bd9413a15b1 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Fri, 15 Nov 2019 19:54:52 +0800 Subject: [PATCH] MLK-23000-3 ARM64: dts: imx8qxp: add mlb dts Add mlb dts file for imx8qxp-lpddr4-val platform. Signed-off-by: Clark Wang Acked-by: Fugang Duan --- arch/arm64/boot/dts/freescale/Makefile | 3 +- .../boot/dts/freescale/imx8-ss-conn.dtsi | 28 +++++++++++++++++++ .../dts/freescale/imx8qxp-lpddr4-val-mlb.dts | 14 ++++++++++ .../boot/dts/freescale/imx8qxp-lpddr4-val.dts | 14 ++++++++++ 4 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f2fd08ab31bd..ad4729d2735e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640 imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \ imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ - imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb + imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \ + imx8qxp-lpddr4-val-mlb.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 5e243ae244d6..fe4af9a31dc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -152,6 +152,20 @@ conn_subsys: bus@5b000000 { status = "disabled"; }; + mlb: mlb@5b060000 { + compatible = "fsl,imx8qxp-mlb150"; + reg = <0x5B060000 0x10000>; + interrupt-parent = <&gic>; + interrupts = , + ; + clocks = <&mlb_lpcg 0>, + <&mlb_lpcg 1>, + <&mlb_lpcg 2>; + clock-names = "mlb", "hclk", "ipg"; + power-domains = <&pd IMX_SC_R_MLB_0>; + status = "disabled"; + }; + usb3phynop1: usb3-phy { compatible = "usb-nop-xceiv"; clocks = <&usb3_lpcg 4>; @@ -261,6 +275,20 @@ conn_subsys: bus@5b000000 { power-domains = <&pd IMX_SC_R_ENET_1>; }; + mlb_lpcg: clock-controller@5b260000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b260000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>, + <&conn_axi_clk>, + <&conn_ipg_clk>; + bit-offset = <0 20 16>; + clock-output-names = "mlb_lpcg_clk", + "mlb_lpcg_hclk", + "mlb_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MLB_0>; + }; + usb2_lpcg: clock-controller@5b270000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b270000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts new file mode 100644 index 000000000000..f4a180867eae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mlb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&esai0 { + status = "disabled"; +}; + +&mlb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts index b99b3786cf05..0cd8105282a5 100755 --- a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts @@ -209,6 +209,12 @@ }; }; +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -384,6 +390,14 @@ >; }; + pinctrl_mlb: mlbgrp { + fsl,pins = < + IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG 0x21 + IMX8QXP_ESAI0_FST_CONN_MLB_CLK 0x21 + IMX8QXP_ESAI0_TX0_CONN_MLB_DATA 0x21 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -- 2.17.1