From 5d50c6a3691051f3dfbb675b91d823a99eeb1cf6 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 11 Jul 2017 11:19:49 +0800 Subject: [PATCH] MLK-15949-2 ARM64: dts: fsl-imx8qxp: correct USDHC per clock rate Set USDHC2/3 per clock's parent clock to 200MHz. Signed-off-by: Haibo Chen --- arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index eec7beb56e5e..1827c545ec91 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -1556,7 +1556,8 @@ <&clk IMX8QXP_SDHC1_CLK>, <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; - assigned-clock-rates = <400000000>, <200000000>, <0>; + assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-rates = <200000000>; power-domains = <&pd_conn_sdch1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; @@ -1572,7 +1573,8 @@ <&clk IMX8QXP_SDHC2_CLK>, <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; - assigned-clock-rates = <400000000>, <200000000>, <0>; + assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-rates = <200000000>; power-domains = <&pd_conn_sdch2>; status = "disabled"; }; -- 2.17.1