From 5856aa4efcd5b3d0947406692a06900b72b47229 Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Fri, 1 Mar 2019 10:27:25 +0200 Subject: [PATCH] MLK-20718-1: clk: imx8qm: Add DSI phy_ref clock Add the missing clocks for the DSI PHY_REF: IMX8QM_MIPI0_DSI_PHY_CLK and IMX8QM_MIPI1_DSI_PHY_CLK. Signed-off-by: Robert Chiras Reviewed-by: Laurentiu Palcu --- drivers/clk/imx/clk-imx8qm.c | 4 ++++ include/dt-bindings/clock/imx8qm-clock.h | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 8b4dd862f7a6..3685b85df7e1 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -346,11 +346,13 @@ static int imx8qm_clk_probe(struct platform_device *pdev) clks[IMX8QM_MIPI0_PWM0_DIV] = imx_clk_divider_scu("mipi0_pwm0_div", SC_R_MIPI_0_PWM_0, SC_PM_CLK_PER); clks[IMX8QM_MIPI0_DSI_TX_ESC_DIV] = imx_clk_divider_scu("mipi0_dsi_tx_esc_div", SC_R_MIPI_0, SC_PM_CLK_MST_BUS); clks[IMX8QM_MIPI0_DSI_RX_ESC_DIV] = imx_clk_divider_scu("mipi0_dsi_rx_esc_div", SC_R_MIPI_0, SC_PM_CLK_SLV_BUS); + clks[IMX8QM_MIPI0_DSI_PHY_DIV] = imx_clk_divider_scu("mipi0_dsi_phy_div", SC_R_MIPI_0, SC_PM_CLK_PHY); clks[IMX8QM_MIPI0_PXL_DIV] = imx_clk_divider_scu("mipi0_pxl_div", SC_R_MIPI_0, SC_PM_CLK_PER); clks[IMX8QM_MIPI1_BYPASS_CLK] = imx_clk_divider_scu("mipi1_bypass_clk", SC_R_MIPI_1, SC_PM_CLK_BYPASS); clks[IMX8QM_MIPI1_PWM0_DIV] = imx_clk_divider_scu("mipi1_pwm0_div", SC_R_MIPI_1_PWM_0, SC_PM_CLK_PER); clks[IMX8QM_MIPI1_DSI_TX_ESC_DIV] = imx_clk_divider_scu("mipi1_dsi_tx_esc_div", SC_R_MIPI_1, SC_PM_CLK_MST_BUS); clks[IMX8QM_MIPI1_DSI_RX_ESC_DIV] = imx_clk_divider_scu("mipi1_dsi_rx_esc_div", SC_R_MIPI_1, SC_PM_CLK_SLV_BUS); + clks[IMX8QM_MIPI1_DSI_PHY_DIV] = imx_clk_divider_scu("mipi1_dsi_phy_div", SC_R_MIPI_1, SC_PM_CLK_PHY); clks[IMX8QM_MIPI1_PXL_DIV] = imx_clk_divider_scu("mipi1_pxl_div", SC_R_MIPI_1, SC_PM_CLK_PER); /* Fixed clocks. */ @@ -733,6 +735,7 @@ static int imx8qm_clk_probe(struct platform_device *pdev) clks[IMX8QM_MIPI0_PWM0_CLK] = imx_clk_gate_scu("mipi0_pwm0_clk", "mipi0_pwm0_div", SC_R_MIPI_0_PWM_0, SC_PM_CLK_PER, NULL, 0, 0); clks[IMX8QM_MIPI0_DSI_TX_ESC_CLK] = imx_clk_gate_scu("mipi0_dsi_tx_esc_clk", "mipi0_dsi_tx_esc_div", SC_R_MIPI_0, SC_PM_CLK_MST_BUS, NULL, 0, 0); clks[IMX8QM_MIPI0_DSI_RX_ESC_CLK] = imx_clk_gate_scu("mipi0_dsi_rx_esc_clk", "mipi0_dsi_rx_esc_div", SC_R_MIPI_0, SC_PM_CLK_SLV_BUS, NULL, 0, 0); + clks[IMX8QM_MIPI0_DSI_PHY_CLK] = imx_clk_gate_scu("mipi0_dsi_phy_clk", "mipi0_dsi_phy_div", SC_R_MIPI_0, SC_PM_CLK_PHY, NULL, 0, 0); clks[IMX8QM_MIPI0_PXL_CLK] = imx_clk_gate_scu("mipi0_pxl_clk", "mipi0_pxl_div", SC_R_MIPI_0, SC_PM_CLK_PER, NULL, 0, 0); clks[IMX8QM_MIPI1_LIS_IPG_CLK] = imx_clk_gate2_scu("mipi1_lis_ipg_clk", "mipi1_clk_root", LPCG_ADDR(MIPI_DSI_1_LPCG + 0x0), 0, FUNCTION_NAME(PD_MIPI_1_DSI)); @@ -748,6 +751,7 @@ static int imx8qm_clk_probe(struct platform_device *pdev) clks[IMX8QM_MIPI1_PWM0_CLK] = imx_clk_gate_scu("mipi1_pwm0_clk", "mipi1_pwm0_div", SC_R_MIPI_1_PWM_0, SC_PM_CLK_PER, NULL, 0, 0); clks[IMX8QM_MIPI1_DSI_TX_ESC_CLK] = imx_clk_gate_scu("mipi1_dsi_tx_esc_clk", "mipi1_dsi_tx_esc_div", SC_R_MIPI_1, SC_PM_CLK_MST_BUS, NULL, 0, 0); clks[IMX8QM_MIPI1_DSI_RX_ESC_CLK] = imx_clk_gate_scu("mipi1_dsi_rx_esc_clk", "mipi1_dsi_rx_esc_div", SC_R_MIPI_1, SC_PM_CLK_SLV_BUS, NULL, 0, 0); + clks[IMX8QM_MIPI1_DSI_PHY_CLK] = imx_clk_gate_scu("mipi1_dsi_phy_clk", "mipi1_dsi_phy_div", SC_R_MIPI_1, SC_PM_CLK_PHY, NULL, 0, 0); clks[IMX8QM_MIPI1_PXL_CLK] = imx_clk_gate_scu("mipi1_pxl_clk", "mipi1_pxl_div", SC_R_MIPI_1, SC_PM_CLK_PER, NULL, 0, 0); /* Display controller */ diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h index 152399fdf4a4..820ea0dcc3d5 100644 --- a/include/dt-bindings/clock/imx8qm-clock.h +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -855,6 +855,12 @@ #define IMX8QM_AUD_DSP_CORE_CLK 794 #define IMX8QM_AUD_OCRAM_IPG 795 -#define IMX8QM_CLK_END 796 +/* MIPI DSI */ +#define IMX8QM_MIPI0_DSI_PHY_DIV 796 +#define IMX8QM_MIPI0_DSI_PHY_CLK 797 +#define IMX8QM_MIPI1_DSI_PHY_DIV 798 +#define IMX8QM_MIPI1_DSI_PHY_CLK 799 + +#define IMX8QM_CLK_END 800 #endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */ -- 2.17.1