From 55379f6b14de85ea2815197eb7fa8fdc3aaf8d68 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 5 Jan 2020 19:21:26 -0800 Subject: [PATCH] MLK-23196 imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM. Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus clocks to OD frequency before it increases ARM voltage. So to conform to the limitation, we'd better increases VDD_ARM to OD voltage in SPL. Signed-off-by: Ye Li Reviewed-by: Anson Huang (cherry picked from commit f9fdb7a6134d8929c2291303c006f7380d97faa8) (cherry picked from commit 543a0f1fdc2009fb24436b14a0488408c2f8341f) --- board/freescale/imx8mp_evk/spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index a5103261ea..7b814db17f 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -88,6 +88,10 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + /* set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); -- 2.17.1