From 5501206a73962107ad134205f31301e2ac4eab2c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Jun 2017 14:08:53 +0800 Subject: [PATCH] MLK-15142-5: imx: imx8m: add soc initialization code Add soc level initialization code. Add arch_cpu_init. Add M4 boot. Add timer_init. Add cpuinfo Add dummy SoC ID. Signed-off-by: Peng Fan Reviewed-by: Ye Li --- arch/arm/cpu/armv8/imx8m/Makefile | 2 +- arch/arm/cpu/armv8/imx8m/soc.c | 191 ++++++++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 2 + arch/arm/include/asm/arch-imx8m/gpio.h | 12 ++ arch/arm/include/asm/arch-imx8m/sys_proto.h | 7 + arch/arm/include/asm/imx-common/iomux-v3.h | 22 ++- arch/arm/include/asm/imx-common/sys_proto.h | 1 + 7 files changed, 235 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/imx8m/soc.c create mode 100644 arch/arm/include/asm/arch-imx8m/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8m/sys_proto.h diff --git a/arch/arm/cpu/armv8/imx8m/Makefile b/arch/arm/cpu/armv8/imx8m/Makefile index aa8a47265e..bba3202fe0 100644 --- a/arch/arm/cpu/armv8/imx8m/Makefile +++ b/arch/arm/cpu/armv8/imx8m/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += clock.o clock_slice.o +obj-y += clock.o clock_slice.o soc.o diff --git a/arch/arm/cpu/armv8/imx8m/soc.c b/arch/arm/cpu/armv8/imx8m/soc.c new file mode 100644 index 0000000000..276fb4782d --- /dev/null +++ b/arch/arm/cpu/armv8/imx8m/soc.c @@ -0,0 +1,191 @@ +/* Copyright 2017 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int timer_init(void) +{ +#ifdef CONFIG_SPL_BUILD + void __iomem *sctr_base = (void __iomem *)SCTR_BASE_ADDR; + unsigned long freq; + u32 val; + + freq = readl(sctr_base + CNTFID0_OFF); + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); + + val = readl(sctr_base + CNTCR_OFF); + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + writel(val, sctr_base + CNTCR_OFF); +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +void reset_cpu(ulong addr) +{ + /* TODO */ + printf("%s\n", __func__); + while (1); +} + +static struct mm_region imx8m_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xB00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + .virt = 0xB00000UL, + .phys = 0xB00000UL, + .size = 0x3f500000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0xC0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x040000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* List terminator */ + 0, + } +}; +struct mm_region *mem_map = imx8m_mem_map; + +u32 get_cpu_rev(void) +{ + /* TODO: */ + return (MXC_CPU_IMX8MQ << 12) | (0 << 4); +} + +#ifdef CONFIG_DISPLAY_CPUINFO +const char *get_imx8m_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8MQ: + return "8MQ"; /* i.MX8 Quad MAX */ + default: + return "??"; + } +} + +const char *get_imx8m_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + default: + return "?"; + } +} + +int print_cpuinfo(void) +{ + u32 cpurev; + cpurev = get_cpu_rev(); + + printf("CPU: i.MX%s rev%s at %d MHz\n", + get_imx8m_type((cpurev & 0xFF000) >> 12), + get_imx8m_rev((cpurev & 0xFFF)), + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + return 0; +} +#endif + +int arch_cpu_init(void) +{ + /* + * Init timer at very early state, because sscg pll setting + * will use it + */ + timer_init(); + clock_init(); + + return 0; +} + +#if defined(CONFIG_FEC_MXC) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[9]; + struct fuse_bank9_regs *fuse = + (struct fuse_bank9_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->mac_addr1); + mac[0] = (value >> 8); + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; +} +#endif + +#ifdef CONFIG_IMX_BOOTAUX +#define M4RCR (0xC) +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + u32 stack, pc; + u32 val; + + if (!boot_private_data) + return -EINVAL; + + stack = *(u32 *)boot_private_data; + pc = *(u32 *)(boot_private_data + 4); + + /* Set the stack and pc to M4 bootROM */ + writel(stack, M4_BOOTROM_BASE_ADDR); + writel(pc, M4_BOOTROM_BASE_ADDR + 4); + + /* Enable M4 */ + val = readl(SRC_BASE_ADDR + M4RCR); + val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK; + val |= SRC_SCR_M4_ENABLE_MASK; + writel(val, SRC_BASE_ADDR + M4RCR); + + return 0; +} + +int arch_auxiliary_core_check_up(u32 core_id) +{ + unsigned val; + + val = readl(SRC_BASE_ADDR + M4RCR); + + if (val & 0x00000001) + return 0; /* assert in reset */ + + return 1; +} +#endif diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index e84621bc3d..510f2aa021 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -29,12 +29,14 @@ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_IMX8DX 0x93 /* dummy ID */ +#define MXC_CPU_IMX8MQ 0xA1 /* dummy ID */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 #define MXC_SOC_MX7ULP 0x80 /* dummy */ #define MXC_SOC_IMX8 0x90 /* dummy */ +#define MXC_SOC_IMX8M 0xA0 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-imx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h new file mode 100644 index 0000000000..73616c4267 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/gpio.h @@ -0,0 +1,12 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8M_GPIO_H +#define __ASM_ARCH_IMX8M_GPIO_H + +#include + +#endif /* __ASM_ARCH_MX7_GPIO_H */ diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h new file mode 100644 index 0000000000..750e90ccc8 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 7587cbbf95..f45ff0fec1 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_MX7 +#ifdef CONFIG_ARCH_IMX8M +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) + +#define PAD_CTL_FSEL0 (0x0 << 3) +#define PAD_CTL_FSEL1 (0x1 << 3) +#define PAD_CTL_FSEL2 (0x2 << 3) +#define PAD_CTL_FSEL3 (0x3 << 3) + +#define PAD_CTL_ODE (0x1 << 5) +#define PAD_CTL_PUE (0x1 << 6) +#define PAD_CTL_HYS (0x1 << 7) +#define PAD_CTL_LVTTL (0x1 << 8) + +#elif defined CONFIG_MX7 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 1f275e391e..c0c74d8b45 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -29,6 +29,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) -- 2.17.1