From 54224157d2ede2ddf7ae250289be956672ca4a5c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 11 Mar 2016 15:44:01 +0800 Subject: [PATCH] MLK-12534 mx6: shutdown vddpu and PCIE phy to save power Shutdown VDDPU and PCIE phy to save power. For PCIE, the i.MX6SL and i.MX6UL does not have this module, so don't need it. For VDDPU, the i.MX6UL does not have GPU, does not need it. And on i.MX6QP there is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Reference: commit: 6b0787b726e2ff32210d742d93ecd3f4bb2ae402 commit: 4bd0032c0eba50fa0caf43f50f735a3cfbe36a8d Signed-off-by: Ye Li (cherry picked from commit 5c96ea91fe89c67991c929c9b39ffaa940d28391) (cherry picked from commit 6a5442b41ef400edd0b332962a3450e909b85df5) (cherry picked from commit 2d7e33530f9bea23c7d09e5b6ae27b0e17f0aa94) (cherry picked from commit 9043e88a78d303091788952c2e1d35fe9544625e) (cherry picked from commit 20b75bb074792d55f4fa556425d30871ef5095aa) --- arch/arm/mach-imx/mx6/soc.c | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index c3a441b79c..15337921cf 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -409,6 +409,40 @@ static void noc_setup(void) } #endif +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val; + + /* need to power down xPU in GPC before turn off PU LDO */ + val = readl(GPC_BASE_ADDR + 0x260); + writel(val | 0x1, GPC_BASE_ADDR + 0x260); + + val = readl(GPC_BASE_ADDR + 0x0); + writel(val | 0x1, GPC_BASE_ADDR + 0x0); + while (readl(GPC_BASE_ADDR + 0x0) & 0x1) + ; + + /* disable VDDPU */ + val = 0x3e00; + writel(val, &anatop->reg_core_clr); +} + +static void imx_set_pcie_phy_power_down(void) +{ + u32 val; + + if (!is_cpu_type(MXC_CPU_MX6SX)) { + val = readl(IOMUXC_BASE_ADDR + 0x4); + val |= 0x1 << 18; + writel(val, IOMUXC_BASE_ADDR + 0x4); + } else { + val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); + val |= 0x1 << 30; + writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); + } +} + int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -484,6 +518,14 @@ int arch_cpu_init(void) if (is_mx6sx()) setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); + if (!is_mx6sl() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_pcie_phy_power_down(); + + if (!is_mx6dqp() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_vddpu_power_down(); + init_src(); #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) -- 2.17.1