From 53ff2641a817099e1c6d1aef409ba004c3a9f1ea Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 13 Nov 2017 23:34:55 +0000 Subject: [PATCH] drm/i915/cnl: only divide up base frequency with crystal source We apply this logic to Gen9 as well. We didn't notice this issue as most part we've encountered so far only use the crystal as source for their timestamp registers. Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to userspace") Reviewed-by: Paulo Zanoni Signed-off-by: Lionel Landwerlin Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-5-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/intel_device_info.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 02f8bf101ccd..405d70124a46 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -403,15 +403,15 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) freq = f24_mhz; break; } - } - /* Now figure out how the command stream's timestamp register - * increments from this frequency (it might increment only - * every few clock cycle). - */ - freq >>= 3 - ((rpm_config_reg & - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + /* Now figure out how the command stream's timestamp + * register increments from this frequency (it might + * increment only every few clock cycle). + */ + freq >>= 3 - ((rpm_config_reg & + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + } return freq; } -- 2.17.1