From 4f8c8854fbec3a87edf9b0cdc1e9c459de3e565e Mon Sep 17 00:00:00 2001 From: Han Xu Date: Thu, 18 May 2017 10:46:53 -0500 Subject: [PATCH] MLK-15052-1: ARM64: dts: add flexspi in 8qxp device tree add the flexspi device tree node for i.mx8qxp Signed-off-by: Han Xu Acked-by: Frank Li --- .../dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts | 36 +++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 14 ++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts index 49f883e0c71b..1077482b7ef4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts @@ -209,6 +209,27 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + pinctrl_lpi2c1: lpi1cgrp { fsl,pins = < SC_P_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000020 @@ -366,6 +387,21 @@ status = "okay"; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + &i2c0_csi0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index 00477b5a598c..39d3c5580647 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -1178,6 +1178,20 @@ power-domains = <&pd_esai0>; status = "disabled"; }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, + <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clock-rates = <29000000>,<29000000>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; }; &A35_0 { -- 2.17.1