From 4ecbda4283cef0dd59484126e22c691901c9990b Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Fri, 1 Mar 2019 10:35:32 +0200 Subject: [PATCH] MLK-20718-3: arm64: dts: imx8dx: Use DSI PHY_REF clk Until now, the DSI PHY_REF clock was by default ON in SCFW, which made this clock unusable in kernel, therefore, this clock was set as CLK_DUMMY in DSI device nodes. Sinnce this clock was set to OFF in SCFW, now it can be used from kernel, so add it to device nodes so that the driver can use it properly. Signed-off-by: Robert Chiras Reviewed-by: Laurentiu Palcu --- arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index f42639c9a3f0..3392f923d99e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1872,17 +1872,19 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&irqsteer_mipi_lvds0>; clocks = - <&clk IMX8QXP_MIPI0_BYPASS_CLK>, + <&clk IMX8QXP_MIPI0_DSI_PHY_CLK>, <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; clock-names = "phy_ref", "tx_esc", "rx_esc"; assigned-clocks = + <&clk IMX8QXP_MIPI0_DSI_PHY_SEL>, <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>, <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>, <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; - assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-rates = <0>, <0>, <0>, <18000000>, <72000000>; assigned-clock-parents = + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>; power-domains = <&pd_mipi_dsi0>; @@ -1902,7 +1904,7 @@ clocks = <&clk IMX8QXP_MIPI0_PIXEL_CLK>, <&clk IMX8QXP_MIPI0_BYPASS_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_MIPI0_DSI_PHY_CLK>; clock-names = "pixel", "bypass", "phy_ref"; power-domains = <&pd_mipi_dsi0>; csr = <&mipi_dsi_csr1>; @@ -2048,17 +2050,19 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&irqsteer_mipi_lvds1>; clocks = - <&clk IMX8QXP_MIPI1_BYPASS_CLK>, + <&clk IMX8QXP_MIPI1_DSI_PHY_CLK>, <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; clock-names = "phy_ref", "tx_esc", "rx_esc"; assigned-clocks = + <&clk IMX8QXP_MIPI1_DSI_PHY_SEL>, <&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>, <&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>, <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; - assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-rates = <0>, <0>, <0>, <18000000>, <72000000>; assigned-clock-parents = + <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>; power-domains = <&pd_mipi_dsi1>; @@ -2078,7 +2082,7 @@ clocks = <&clk IMX8QXP_MIPI1_PIXEL_CLK>, <&clk IMX8QXP_MIPI1_BYPASS_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_MIPI1_DSI_PHY_CLK>; clock-names = "pixel", "bypass", "phy_ref"; power-domains = <&pd_mipi_dsi1>; csr = <&mipi_dsi_csr2>; -- 2.17.1