From 47447f63cd800f4c8bfb3f2208ccae014c472a76 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 11:18:13 +0800 Subject: [PATCH] MLK-22487-1 clk: imx: clk-pll14xx: unbypass PLL by default When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan --- drivers/clk/imx/clk-pll14xx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index db43dea058a7..87b037c2c6af 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -397,6 +397,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, struct clk *clk; struct clk_init_data init; int len; + u32 val; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -438,6 +439,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, pll->hw.init = &init; pll->type = pll_clk->type; + val = readl_relaxed(pll->base + GNRL_CTL); + val &= ~BYPASS_MASK; + writel_relaxed(val, pll->base + GNRL_CTL); + clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { pr_err("%s: failed to register pll %s %lu\n", -- 2.17.1