From 42b3634e67f529bb70b69f5c4cbbf810933745b2 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Tue, 18 Sep 2018 15:00:52 +0800 Subject: [PATCH] MLK-19610: hdmi rx: Enable hdmi rx edid function Update edid block0&1 for imx8qm hdmi rx. Remove unsupported video modes. Added edid clock setting. Signed-off-by: Sandor Yu --- .../media/platform/imx8/hdmi/mxc-hdmi-hw.c | 56 +++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/imx8/hdmi/mxc-hdmi-hw.c b/drivers/media/platform/imx8/hdmi/mxc-hdmi-hw.c index a6f582c5373d..c7c8ed9fc886 100644 --- a/drivers/media/platform/imx8/hdmi/mxc-hdmi-hw.c +++ b/drivers/media/platform/imx8/hdmi/mxc-hdmi-hw.c @@ -16,30 +16,30 @@ #include "mxc-hdmi-rx.h" u8 block0[128] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, - 0x1e, 0x6d, 0xfd, 0x5a, 0x9b, 0x5f, 0x02, 0x00, - 0x07, 0x19, 0x01, 0x04, 0xb5, 0x3c, 0x22, 0x78, - 0x9f, 0x30, 0x35, 0xa7, 0x55, 0x4e, 0xa3, 0x26, - 0x0f, 0x50, 0x54, 0x21, 0x08, 0x00, 0x71, 0x40, - 0x81, 0x80, 0x81, 0xc0, 0xa9, 0xc0, 0xd1, 0xc0, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x50, 0xd0, - 0x00, 0xa0, 0xf0, 0x70, 0x3e, 0x80, 0x08, 0x90, - 0x65, 0x0c, 0x58, 0x54, 0x21, 0x00, 0x00, 0x1a, - 0x28, 0x68, 0x00, 0xa0, 0xf0, 0x70, 0x3e, 0x80, - 0x08, 0x90, 0x65, 0x0c, 0x58, 0x54, 0x21, 0x00, - 0x00, 0x1a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x28, - 0x3d, 0x87, 0x87, 0x38, 0x01, 0x0a, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, - 0x00, 0x32, 0x37, 0x4d, 0x55, 0x36, 0x37, 0x0a, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xd4 + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, + 0x3B, 0x10, 0xFD, 0x5A, 0x9B, 0x5F, 0x02, 0x00, + 0x19, 0x1C, 0x01, 0x04, 0xB3, 0x3C, 0x22, 0x78, + 0x9F, 0x30, 0x35, 0xA7, 0x55, 0x4E, 0xA3, 0x26, + 0x0F, 0x50, 0x54, 0x20, 0x00, 0x00, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x69, 0x4D, 0x58, 0x38, 0x51, + 0x4D, 0x20, 0x48, 0x44, 0x4D, 0x49, 0x52, 0x58, + 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x28, + 0x3D, 0x87, 0x87, 0x1E, 0x01, 0x0A, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x64 }; u8 block1[128] = { - 0x02, 0x03, 0x11, 0x71, 0x44, 0x90, 0x04, 0x03, - 0x01, 0x23, 0x09, 0x07, 0x07, 0x83, 0x01, 0x00, - 0x00, 0x02, 0x3a, 0x80, 0x18, 0x71, 0x38, 0x2d, - 0x40, 0x58, 0x2c, 0x45, 0x00, 0x58, 0x54, 0x21, - 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x03, 0x13, 0x71, 0x46, 0x90, 0x04, 0x03, + 0x5D, 0x1F, 0x22, 0x23, 0x09, 0x07, 0x07, 0x83, + 0x01, 0x00, 0x00, 0x04, 0x74, 0x00, 0x30, 0xF2, + 0x70, 0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0x20, + 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -50,7 +50,7 @@ u8 block1[128] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x97 }; S_HDMI_SCDC_SET_MSG scdcExampleData = { @@ -270,12 +270,24 @@ static void get_color_depth(struct mxc_hdmi_rx_dev *hdmi_rx, void hdmirx_edid_set(state_struct *state) { struct mxc_hdmi_rx_dev *hdmi_rx = state_to_mxc_hdmirx(state); + GENERAL_Read_Register_response regresp; /* Set EDID - block 0 */ CDN_API_HDMIRX_SET_EDID_blocking(state, 0, 0, &block0[0]); /* Set EDID - block 1 */ CDN_API_HDMIRX_SET_EDID_blocking(state, 0, 1, &block1[0]); dev_dbg(&hdmi_rx->pdev->dev, "EDID block 0/1 set complete.\n"); + + /* Read the current value of the CTRL register */ + CDN_API_General_Read_Register_blocking(state, 0xb000, ®resp); + /* Clear the 'divisor_a' and 'divisor_b' values - bits 15:8 */ + regresp.val &= ~0xFF00; + /* Set the 'divisor_a' value */ + regresp.val |= 0x4 << 14; + /* Set the 'divisor_b' value */ + regresp.val |= 0x32 << 8; + /* Write the CTRL register back */ + CDN_API_General_Write_Register_blocking(state, 0xb000, regresp.val); } /* Set SCDC data sample */ -- 2.17.1